Display apparatus and driving method thereof

Patent metadata

Field	Value
Publication number	US-10290246-B2
Application number	US-201715498191-A
Country	US
Kind code	B2
Filing date	Apr 26, 2017
Priority date	Apr 27, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A display apparatus includes a plurality of pixels for receiving a plurality of gate signals, and a plurality of data voltages, a level shifter for receiving a gate driving voltage and a plurality of gate control clocks to generate a plurality of reference clocks, and for generating a plurality of control clocks by delaying the reference clocks by a predetermined time, a gate driver for outputting the gate signals in response to the control clocks, a short circuit protector for sensing a current of each control clock at each falling edge of each gate control clock to detect a static current of the each control clock, and for outputting a shut-down signal based on a count of the static current detection, and a voltage generator for providing the gate driving voltage to the level shifter, and shutting down in response to the shut-down signal.

First claim

What is claimed is:

1. A display apparatus comprising:
a plurality of pixels configured to receive a plurality of gate signals, and a plurality of data voltages;
a level shifter configured to receive a gate driving voltage and a plurality of gate control clocks to generate a plurality of reference clocks, and configured to generate a plurality of control clocks by delaying the plurality of reference clocks by a predetermined time period to generate a plurality of control clocks;
a gate driver configured to output the plurality of gate signals in response to the plurality of control clocks;
a short circuit protector configured to sense a current of each of the control clocks at each falling edge of each of the plurality of gate control clocks to detect a static current of each of the plurality of control clocks, and configured to output a shut-down signal based on a count value by counting the detection of the static current of each of the plurality of control clocks; and
a voltage generator configured to provide the gate driving voltage to the level shifter, and shut down in response to the shut-down signal.

2. The display apparatus of claim 1 , wherein the short circuit protector outputs the shut-down signal when the count value is greater than a reference count value.

3. The display apparatus of claim 1 , wherein a (k+1)-th gate control clock is a signal that is a k-th gate control clock delayed by a first time period, the k-th gate control clock has a first period, and the k is a natural number.

4. The display apparatus of claim 3 , wherein the period of a k-th reference clock is set to a second period that is twice of the first period, a rising edge of the k-th reference clock is synchronously set to a p-th rising edge of the k-th gate control clock, and a falling edge of the k-th reference clock is synchronously set to a (p+1)-th rising edge of the k-th gate control clock.

5. The display apparatus of claim 4 , wherein a k-th control clock is generated by delaying the k-th reference clock by a second time period, and the second time period is greater than zero and less than one-fifth of an activated time period of the k-th gate control clock.

6. The display apparatus of claim 5 , wherein the second time period is set to 100 ns.

7. The display apparatus of claim 5 , wherein the level shifter comprises:
a clock generator configured to receive the gate driving voltage and the gate control clocks to generate the reference clocks; and
a clock delayer configured to delay the reference clocks by the second time period to generate the control clocks.

8. The display apparatus of claim 5 , wherein the short circuit protector comprises:
a current sensor configured to receive the gate control clocks, and sense the current of each of the control clocks at the falling edge of corresponding each of the gate control clocks;
a static current detector configured to detect the static current in the sensed current;
an error counter configured to count the detection of the static current, and output a short circuit signal when the count value is greater than the reference count value; and
a short circuit determiner configured to output the shut-down signal in response to the short circuit signal.

9. The display apparatus of claim 8 , wherein
each of the reference clocks comprises:
a plurality of reference clock signals generated by the gate control clocks; and
a plurality of reference clock bar signals generated by the gate control clocks, and having phases respectively opposite to phases of the reference clock signals, and
each of the control clocks comprises:
a plurality of clock signals generated by delaying the reference clock signals by the second time period; and
a plurality of clock bar signals generated by delaying the reference clock bar signals by the second time period.

10. The display apparatus of claim 9 , wherein the current sensor senses a current of a k-th clock signal and a current of a k-th clock bar signal at each falling edge of the k-th gate control clock.

11. The display apparatus of claim 9 , wherein, when a count value by counting detection of the static current of at least one of the clock signals and the clock bar signals is greater than the reference count value, the short circuit determiner outputs the shut-down signal.

12. The display apparatus of claim 8 , wherein the error counter is configured to receive a start signal pulse for driving the gate driver, reset the count value in response to the start signal pulse, and perform the counting.

13. A driving method of a display apparatus comprising:
generating a plurality of reference clocks using a gate driving voltage and a plurality of gate control clocks;
generating a plurality of control clocks by delaying the reference clocks by a predetermined time period;
sensing a current of each of the control clocks at each falling edge of each of the gate control clocks;
detecting a static current in the sensed current;
counting the detection of the static current when the static current is detected;
shutting down a voltage generator for generating the gate driving voltage when the count value is greater than a reference count value; and
generating a plurality of gate signals using the control clocks, and applying the gate signals and a plurality of data voltages to pixels, when the count value is less than or equal to the reference count value.

14. The driving method of a display apparatus of claim 13 , wherein a (k+1)-th gate control clock is a signal that is a k-th gate control clock delayed by a first time period, the k-th gate control clock has a first period, and the k is a natural number.

15. The driving method of a display apparatus of claim 14 , wherein the period of a k-th reference clock is set to a second period that is twice of the first period, a rising edge of the k-th reference clock is synchronously set to a p-th rising edge of the k-th gate control clock, and a falling edge of the k-th reference clock is synchronously set to a (p+1)-th rising edge of the k-th gate control clock.

16. The driving method of a display apparatus of claim 15 , wherein a k-th control clock is generated by delaying the k-th reference clock by a second time period, and the second time period is greater than zero, and less than one-fifth of an activated time period of the k-th gate control clock.

17. The driving method of a display apparatus of claim 16 , wherein
each of the reference clocks comprises:
a plurality of reference clock signals generated by the gate control clocks; and
a plurality of reference clock bar signals generated by the gate control clocks, and having phases respectively opposite to phases of the reference clock signals, and
each of the control clocks comprises:
a plurality of clock signals generated by delaying the reference clock signals by the second time period; and
a plurality of clock bar signals generated by delaying the reference clock bar signals by the second time period.

18. The driving method of a display apparatus of claim 17 , wherein a current of a k-th clock signal and a current of a k-th clock bar signal are sensed at each falling edge of the k-th gate control clock.

19. The driving method of a display apparatus of claim 17 , wherein, when a count value by counting detection of the static current of at least one of the clock signals and the clock bar signals is greater than the reference count value, the voltage generator becomes shut down.

20. The driving method of a display apparatus of claim 13

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jongjae
• Lee Seokhwan
• Lee Dae-Sik
• Heo Seyoung

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title