On-die termination circuit and on-die termination method

Patent metadata

Field	Value
Publication number	US-2016134285-A1
Application number	US-201514742219-A
Country	US
Kind code	A1
Filing date	Jun 17, 2015
Priority date	Nov 12, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

An ODT circuit capable of generating an OCD/ODT code and/or a reference voltage adaptively adjusted according to a system environment is disclosed. The ODT circuit comprises a system environment detector, an OCD/ODT replica circuit, an OCD/ODT code generator and an OCD/ODT unit. The system environment detector detects a supply voltage to generate a voltage code, detects an operating temperature to generate a temperature code, and detects an operating frequency to generate a frequency code. The OCD/ODT code generator generates a pull-up code and a pull-down code currently optimized for a semiconductor memory device based on a pull-up reference voltage, a pull-down reference voltage, the voltage code, the temperature code and the frequency code.

First claim

1 . An on-die termination (ODT) circuit, comprising:
a system environment detector configured to,
detect a supply voltage to generate voltage code,
detect an operating temperature to generate a temperature rode, and
detect an operating frequency to generate a frequency code;
an on-chip driver (OCD)/ODT replica circuit configured to generate a pull-up reference voltage and a pull-down reference voltage; an OCD/ODT code generator configured to,
generate an initial code based on the pull-up reference voltage, the pull-down reference voltage, the voltage code, the temperature code and the frequency code, and
generate a pull-up code and a pull-down code based on the initial code, the voltage code, the temperature code and the frequency code; and
an OCD/ODT circuit configured to change ODT resistance based on the pull-up code and the pull-down code.

2 . The ODT circuit of claim 1 , wherein the system environment detector comprises:
a voltage detecting circuit configured to detect the supply voltage to generate the voltage code; a temperature detecting circuit configured to detect the operating temperature to generate the temperature code; and a frequency detecting circuit configured to detect the operating frequency to generate the frequency code.

3 . The ODT circuit of claim 2 , wherein the voltage detecting circuit comprises:
a reference voltage generator configured to generate a first reference voltage and a second reference voltage; a voltage divider configured to divide the supply voltage to generate a first voltage, a first comparator configured to generate a first comparison output voltage based on the first voltage and the first reference voltage; a second comparator configured to generate a second comparison output voltage based on the first voltage and the second reference voltage; and a decoder configured to decode the first comparison output voltage and the second comparison output voltage to generate the voltage code.

4 . The ODT circuit of claim 3 , wherein
the voltage code includes a first voltage, a second voltage code, and a third voltage code, the first voltage code has a voltage level greater than a first supply voltage, the second voltage code has a voltage level greater than or equal to a second supply voltage and smaller than or equal to the first supply voltage, and the third voltage code has a voltage level smaller than a second supply voltage.

5 . The ODT circuit of claim 2 , wherein the temperature detecting circuit comprises:
a band-gap reference circuit configured to generate a first sense signal having a voltage level proportional to an absolute value of the operating temperature and a second sense signal having a voltage level inversely proportional to the absolute value; a first current-controlled oscillator configured to generate a first clock signal based on the first sense signal; a second current-controlled oscillator configured to generate a second clock signal based on the second sense signal; a first counter configured to count the second clock signal to generate a selection signal; and a second counter configured to count the first clock signal to generate the temperature code in response to the selection signal.

6 . The ODT circuit of claim 5 , wherein the first current controlled oscillator comprises:
a voltage-current converter configured to generate a first current signal corresponding to the first sense signal; and an oscillator configured to generate the first clock signal such that the first clock signal oscillates in response to the first current signal.

7 . The ODT circuit of claim 5 , wherein the second current-controlled oscillator comprises:
a voltage-current converter configured to genes ale a second current signal corresponding to the second sense signal; and an oscillator configured to generate the second clock signal such that the second clock signal oscillates in response to the second current signal.

8 . The ODT circuit of claim 2 , wherein the frequency detecting circuit comprises:
a frequency divider configured to frequency-divide a first clock signal to generate a second clock signal; a gated oscillator configured to generate a third clock signal based on the second clock signal; and a counter and decoder figured to count and decode the third clock signal to generate the frequency code.

9 . The ODT circuit of claim 1 , wherein the OCD/ODT code generator comprises:
an OCD/ODT code generating unit configured to,
generate the initial code based on the pull-up reference voltage, the pull-down reference voltage, the voltage code, the temperature code and the frequency code, and
generate the pull-up code and the pull-down code based on an adjusted code; and
a code adjusting circuit configured to,
generate the adjusted code based on the initial code, the voltage code, the temperature code and the frequency code, and
provide the adjusted code to the OCD/ODT code generating unit.

10 . The ODT circuit of claim 9 , wherein the code adjusting circuit comprises:
an adder configured to add the initial code and a compensation code to generate a first output signal; a subtractor configured to subtract the initial code from the compensation code to generate a second output signal; and a selecting circuit configured to,
select one of the first output signal and the second output signal in response to the voltage code, the temperature code and the frequency code, and
output the selected signal as the adjusted code.

11 . The ODT circuit of claim 9 , wherein the code adjusting circuit comprises:
a plurality of code registers configured to store stored values therein, the stored values being sequentially offset by a number from the initial code; and a selecting circuit configured to select one of the output signals of the code registers in response to the voltage code, the temperature code and the frequency code, and output the selected signal as the adjusted code.

12 . The ODT circuit of claim 1 , wherein the OCD/ODT code generator comprises:
an OCD/ODT code generating unit configured to generate the initial code based on the pull-up reference voltage, the pull-down reference voltage, the voltage code, the temperature code and the frequency code; and a code adjusting circuit configured to generate the pull-up code and the pull-down code based on the initial code, the voltage code, the temperature code and the frequency code.

13 . An on-die termination (ODT) circuit, comprising:
a system environment detector configured to,
detect a supply voltage to generate a voltage code,
detect an operating temperature to generate a temperature code, and
detect an operating frequency to generate a frequency code;
an on-chip driver (OCD)/ODT replica circuit configured to generate a pull-up reference voltage and a pull-down reference voltage; an OCD/ODT code generator configured to generate a pull-up code and a pull-down code based on the pull-up reference voltage, the pull-down reference voltage, the voltage code, the temperature code and the frequency code; an OCD/ODT circuit configured to change OUT resistance in response to the pull-up code and the pull-down code; an input/output (I/O) pad connected to the OCD/ODT unit, the I/O pad configured to generate a first input; a reference voltage generator configured to generate a reference voltage based on the voltage code, the temperature code and the frequency code; and a comparator configured to generate a second input signal based on the first input and the reference voltage.

14 . The ODT circuit of claim 13 , wherein the second input signal includes one or

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ha Kyung-Soo

Classifications

• H03K19/00369

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title