Liquid crystal display

Patent metadata

Field	Value
Publication number	US-9275591-B2
Application number	US-201414182784-A
Country	US
Kind code	B2
Filing date	Feb 18, 2014
Priority date	Mar 2, 2009
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A liquid crystal display includes a gate driver including stages, and a clock generator which receives a clock generation control signal, generates a clock signal and a clock bar signal based on one or more of the clock generation control signal, a gate-on voltage and a gate-off voltage, and outputs the clock signal and the clock bar signal to the gate driver. The clock generator includes an overcurrent protector unit which intercepts at least one of the clock signal and the clock bar signal when a voltage level of at least one of the gate-on voltage and the gate-off voltage is greater than a reference level.

First claim

What is claimed is:

1. A liquid crystal display comprising:
a gate driver including stages; and
a clock generator which receives a single gate clock signal and generates a clock signal and a clock bar signal based on the single gate clock signal and outputs the clock signal and the clock bar signal to the gate driver,
wherein
the clock signal and the clock bar signal are each delayed for a same predetermined time from a previous clock signal and a previous clock bar signal, respectively, based on a time delay signal received by the clock generator, and
the clock signal and the clock bar signal include first through third clock signals and first through third clock bar signals, respectively, and
the first through third clock signals and the first through third clock bar signals are each successively outputted, and
the clock generator receives the single gate clock signal and generates the first clock signal and the first clock bar signal, and successively thereafter generates the second clock signal and the second clock bar signal and the third clock signal and the third clock bar signal based on the first clock signal, the first clock bar signal and the time delay signal.

2. The liquid crystal display of claim 1 , wherein
the second clock signal and the second clock bar signal are delayed for a first period of time from the first clock signal and the second clock bar signal based on the time delay signal, and
the third clock signal and the third clock bar signal are delayed for a second period of time, the second period of time being twice as long as the first period of time, from the first clock signal and the first clock bar signal based on the time delay signal.

3. A liquid crystal display comprising:
a gate driver including stages; and
a clock generator which receives a single gate clock signal and generates a clock signal and a clock bar signal based on the single gate clock signal and outputs the clock signal and the clock bar signal to the gate driver,
wherein
the clock signal and the clock bar signal are each delayed for a predetermined time from a previous clock signal and a previous clock bar signal, respectively, based on a time delay signal received by the clock generator,
wherein the clock signal and the clock bar signal include first through third clock signals and first through third clock bar signals, respectively, the first through third clock signals are successively outputted,
the first through third clock bar signals are successively outputted, the clock generator receives the single gate clock signal and generates the first clock signal and the first clock bar signal, the clock generator generates the second clock signal and the second clock bar signal delayed from the first clock signal and the first clock bar signal for a first period of time based on the time delay signal, and the clock generator generates the third clock signal and the third clock bar signal delayed the second clock signal and the second clock bar signal for a second period of time based on the time delay signal.

4. The liquid crystal display of claim 3 , wherein the first period of time is equal to the second period of time.

5. A liquid crystal display comprising:
a gate driver including stages; and
a clock generator which receives first through third clock generation control signals, and generates a first clock signal and a second clock signal based on a gate-on voltage and a gate-off voltage and the second clock signal having a different phase from the first clock signal,
wherein
the clock generator receives the third clock generation control signal at a predetermined time point, the predetermined time point being between a first time point when the gate-on voltage becomes higher than a first reference level and a second time point when the first clock generation control signal is supplied to the clock generator, and
the clock generator outputs the first clock signal and the second clock signal based on the second clock generation control signal at a third time point when the third clock generation control signal becomes higher than a second reference level.

6. The liquid crystal display of claim 5 , wherein
when the second clock generation control signal transitions to a first level at the third time point, the first clock signal and the second clock signal are normally outputted, and
when the second clock generation control signal transitions to a second level, different from the first level, at the third time point, the first clock signal and the second clock signal are not outputted and charge sharing is performed until the second clock generation control signal transitions to the first level.

7. The liquid crystal display of claim 5 , further comprising a voltage generation circuit which receives a power supply voltage and generates the gate-on voltage and the gate-off voltage,
wherein the voltage generation circuit provides a normal voltage state signal to the clock generator for reporting a normal output of the gate-on voltage and the gate-off voltage.

8. The liquid crystal display of claim 7 , wherein
the clock generator receives the normal voltage state signal,
the first clock generation control signal is supplied to the clock generator based on the normal voltage state signal, and
the second time point precedes the first time point.

9. The liquid crystal display of claim 5 , wherein
the first clock generation control signal is an enable signal,
the second clock generation control signal is a gate clock signal, and
the third clock generation control signal is a time delay signal.

10. The liquid crystal display of claim 5 , wherein the second clock signal has a inverse phase of the first clock signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Bang Nam-Suk
• Cho Hyun-Sang
• Park Joo-Hwan
• Chung Jae-Seob

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2330/04

  Display protection · CPC title

• G02F1/133

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title