Power semiconductor module

Patent metadata

Field	Value
Publication number	US-10283454-B2
Application number	US-201715819693-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	May 22, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

The present invention relates to a power semiconductor module, comprising at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor and at least one power semiconductor diode, wherein at least a first substrate is provided for carrying the power semiconductor transistor in a first plane, the first plane lying parallel to the plane of the substrate, wherein the power semiconductor diode is provided in a second plane, wherein the first plane is positioned between the substrate and the second plane in a direction normal to the first plane and wherein the first plane is spaced apart from the second plane in a direction normal to the first plane. The first plane is spaced apart from the second plane in a direction normal to the first plane, whereby the first substrate is based on a direct bonded copper substrate and the first substrate is a direct-bonded copper substrate for carrying the transistor, on which first substrate a layer of a printed circuit board is provided for carrying the diode. Alternatively, the first substrate is a direct-bonded copper substrate for carrying the transistor, on which first substrate a foil is provided for carrying the diode, wherein the foil comprises an electrically insulating main body and an electrically conductive structure provided thereon for carrying the diode. Such a power semiconductor module provides a low stray inductance and/or may be built easily.

First claim

The invention claimed is:

1. A power semiconductor module, comprising:
at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor and at least one power semiconductor diode,
wherein at least a first substrate is provided for carrying the power semiconductor transistor in a first plane, the first plane lying parallel to the plane of the first substrate,
wherein at least a second substrate is provided for carrying the power semiconductor diode, the second substrate being disposed between the first substrate and the power semiconductor diode,
wherein the power semiconductor diode is provided in a second plane, wherein the first plane is positioned between the first substrate and the second plane in a direction normal to the first plane,
wherein the first plane is spaced apart from the second plane in a direction normal to the first plane,
wherein the first substrate is based on a direct bonded copper substrate and the first substrate is a direct-bonded copper substrate for carrying the transistor, and
wherein the second substrate comprises a layer of a printed circuit board for carrying the diode.

2. The power semiconductor module according to claim 1 , wherein the first substrate is connected to a cooling device.

3. The power semiconductor module according to claim 1 , wherein the power semiconductor devices form at least one of a P-cell and an N-cell.

4. The power semiconductor module according to claim 1 , wherein the transistor is formed based on a wide bandgap semiconductor.

5. The power semiconductor module according to claim 1 , wherein the power semiconductor module comprises at least one interposer.

6. The power semiconductor module according to claim 2 , wherein the power semiconductor devices form at least one of a P-cell and an N-cell.

7. The power semiconductor module according to claim 2 , wherein the transistor is formed based on a wide bandgap semiconductor.

8. The power semiconductor module according to claim 2 , wherein the power semiconductor module comprises at least one interposer.

9. The power semiconductor module according to claim 6 , wherein the power semiconductor devices form both a P-cell and an N-cell, wherein the power semiconductor devices of the P-cell are arranged on electrically conductive structures and wherein power semiconductor devices of the N-cell are provided on electrically conductive structures, wherein the electrically conductive structures of the P-cell are separated from the electrically conductive structures of the N-cell.

10. The power semiconductor module according to claim 3 , wherein the power semiconductor devices form both a P-cell and an N-cell, wherein the power semiconductor devices of the P-cell are arranged on electrically conductive structures and wherein power semiconductor devices of the N-cell are provided on electrically conductive structures, wherein the electrically conductive structures of the P-cell are separated from the electrically conductive structures of the N-cell.

11. The power semiconductor module according to claim 3 , wherein the transistor is formed based on a wide bandgap semiconductor.

12. The power semiconductor module according to claim 3 , wherein the power semiconductor module comprises at least one interposer.

13. The power semiconductor module according to claim 10 , wherein the power semiconductor module comprises at least one interposer.

14. The power semiconductor module according to claim 10 , wherein the transistor is formed based on a wide bandgap semiconductor.

15. A power semiconductor module, comprising:
at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor and at least one power semiconductor diode,
wherein at least a first substrate is provided for carrying the power semiconductor transistor in a first plane, the first plane lying parallel to the plane of the first substrate,
wherein at least a second substrate is provided for carrying the power semiconductor diode, the second substrate being disposed between the first substrate and the power semiconductor diode,
wherein the power semiconductor diode is provided in a second plane, wherein the first plane is positioned between the first substrate and the second plane in a direction normal to the first plane,
wherein the first plane is spaced apart from the second plane in a direction normal to the first plane,
wherein the first substrate is based on a direct bonded copper substrate and the first substrate is a direct-bonded copper substrate for carrying the transistor, and
wherein the second substrate comprises a foil for carrying the diode, wherein the foil comprises an electrically insulating main body and an electrically conductive structure provided thereon for carrying the diode,
on which first substrate a foil is provided for carrying the diode, wherein the foil comprises an electrically insulating main body and an electrically conductive structure provided thereon for carrying the diode.

16. The power semiconductor module according to claim 15 , wherein the first substrate is connected to a cooling device.

17. The power semiconductor module according to claim 15 , wherein the power semiconductor devices form at least one of a P-cell and an N-cell.

18. The power semiconductor module according to claim 15 , wherein the transistor is formed based on a wide bandgap semiconductor.

19. The power semiconductor module according to claim 15 , wherein the power semiconductor module comprises at least one interposer.

20. The power semiconductor module according to claim 17 , wherein the power semiconductor devices form both a P-cell and an N-cell, wherein the power semiconductor devices of the P-cell are arranged on electrically conductive structures and wherein power semiconductor devices of the N-cell are provided on electrically conductive structures, wherein the electrically conductive structures of the P-cell are separated from the electrically conductive structures of the N-cell.

Assignees

• Abb Schweiz Ag

Inventors

• Traub Felix
• Mohn Fabian
• Schuderer Juergen
• Kearney Daniel
• Kicin Slavo

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W90/00

  Package configurations · CPC title