Negative capacitance FET with improved reliability performance

Patent metadata

Field	Value
Publication number	US-10276697-B1
Application number	US-201715795610-A
Country	US
Kind code	B1
Filing date	Oct 27, 2017
Priority date	Oct 27, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

First claim

What is claimed is:

1. A device, comprising:
a semiconductor layer;
an interfacial layer disposed over the semiconductor layer;
an amorphous dielectric layer disposed over the interfacial layer;
a ferroelectric layer disposed over the amorphous dielectric layer; and
a metal gate electrode disposed over the ferroelectric layer;
wherein at least one of the following is true:
the interfacial layer is doped;
the amorphous dielectric layer has a nitridized outer surface;
a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or
a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

2. The device of claim 1 , wherein the semiconductor layer includes a fin of a FinFET device.

3. The device of claim 1 , wherein the device includes a negative-capacitance device.

4. The device of claim 1 , wherein the interfacial layer is doped with yttrium or lanthanum.

5. The device of claim 1 , wherein the ferroelectric layer is doped.

6. The device of claim 1 , wherein the ferroelectric layer includes a crystalline structure.

7. The device of claim 6 , wherein the crystalline structure has an orthorhombic orientation.

8. The device of claim 1 , wherein the nitridized outer surface includes hafnium silicon oxynitride.

9. The device of claim 1 , wherein the diffusion-barrier layer includes a metal or a metal oxide.

10. The device of claim 1 , wherein the seed layer includes zirconium oxide.

11. A device, comprising:
a fin structure;
a doped interfacial layer wrapping around the fin structure;
an undoped high-k dielectric layer located over the doped interfacial layer, wherein the undoped high-k dielectric layer has a nitridized outer surface;
a diffusion-barrier layer located over the nitridized outer surface of the undoped high-k dielectric layer;
a seed layer located over the diffusion-barrier layer;
a doped ferroelectric layer located over the seed layer, wherein the doped ferroelectric layer has a crystalline structure; and
a metal gate electrode disposed over the doped ferroelectric layer.

12. A method, comprising:
forming an interfacial layer over a semiconductor layer;
forming a dielectric layer over the interfacial layer;
forming at least a first layer or a second layer over the dielectric layer;
forming a ferroelectric layer over the first layer or over the second layer, wherein the ferroelectric layer includes dopants; and
performing an annealing process after the forming of the ferroelectric layer;
wherein:
the first layer prevents the dopants of the ferroelectric layer from being diffused into the dielectric layer during the performing of the annealing process; and
the second layer serves as a seed layer to facilitate the forming of the ferroelectric layer.

13. The method of claim 12 , further comprising: forming a fin structure as the semiconductor layer, wherein the forming of the interfacial layer is performed such that the interfacial layer wraps around an upper surface and sidewalls of the fin structure.

14. The method of claim 12 , wherein the forming of the interfacial layer comprises doping the interfacial layer.

15. The method of claim 14 , wherein the doping of the interfacial layer comprises doping the interfacial layer with yttrium or lanthanum.

16. The method of claim 12 , wherein the forming of the dielectric layer comprises forming an undoped hafnium oxide layer as the dielectric layer.

17. The method of claim 12 , wherein the forming the at least the first layer or the second layer comprises:
forming the first layer over the dielectric layer; and
forming the second layer over the first layer.

18. The method of claim 17 , wherein the forming of the first layer comprises forming a diffusion-barrier layer as the first layer, and wherein the diffusion-barrier layer is formed to contain a metal or a metal oxide.

19. The method of claim 17 , wherein the forming of the second layer and the forming of the ferroelectric layer are performed such that:
the ferroelectric layer has a crystalline structure; and
the second layer and the ferroelectric layer each have an orthorhombic orientation.

20. The method of claim 12 , further comprising: performing a nitridation process to nitridize an outer surface of the dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chun-Chieh
• Peng Cheng-Yi
• Lee Chien-Hsing
• Yeh Ling-Yen
• Chang Chih-Sheng
• Diaz Carlos H

Classifications

• H10P90/12

  Preparing bulk and homogeneous wafers · CPC title

• H10P14/00

  Formation of materials, e.g. in the shape of layers or pillars · CPC title

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H01L29/516

  Electricity · mapped topic

• H01L27/11585

  Electricity · mapped topic