Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress

Patent metadata

Field	Value
Publication number	US-10276535-B2
Application number	US-201715794192-A
Country	US
Kind code	B2
Filing date	Oct 26, 2017
Priority date	Aug 30, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

First claim

What is claimed is:

1. A method comprising:
patterning a matrix of contact trenches arranged in rows and columns into a mask upon an electronic package structure, the matrix of contact trenches arranged in rows and columns, wherein the matrix of contact trenches comprise: a plurality of first contact trenches each comprising a trench major axis and a trench minor axis and a plurality of second contact trenches each comprising trench diameter axes;
forming a plurality of first contacts by forming conductive material within the plurality of first contact trenches, wherein a surface area of each of the plurality of first contacts decreases radially away from a center of the electronic package structure;
forming a plurality of second contacts by forming conductive material within the plurality of second contact trenches.

2. The method of claim 1 , further comprising:
removing the mask from the electronic package structure.

3. The method of claim 1 , wherein respective neighboring surface areas of the electronic package structure that are exposed by the patterned contact trenches within the same row or within the same column are different.

4. The method of claim 1 , wherein neighboring contact trenches within the same row or within the same column are patterned such that an aspect ratio of respective major axes to minor axes of the neighboring contact trenches are different.

5. The method of claim 1 , wherein neighboring contact trenches within the same row or within the same column are patterned such that an aspect ratio of respective major axes to minor axes of the neighboring contact trenches are the same.

6. The method of claim 1 , wherein the plurality of first contacts are located within a power/ground region of the electronic package structure and the plurality of second contacts are located within an input/output region of the electronic package structure.

7. The method of claim 1 , wherein the plurality of first contacts are located within a quintain of the electronic package structure, and the plurality of second contacts are located within an perimeter region of the electronic package structure that complexly surrounds the quintain.

8. The method of claim 1 , further comprising:
forming a solder interconnect upon the surface area of each of the plurality of first contacts and upon each of the plurality of second contacts.

Assignees

• IBM

Inventors

• Call Anson J
• Khanna Vijayeshwar D
• Russell David J
• Tunga Krishna R

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W20/43

  Layouts of interconnections · CPC title