Reduction of solder interconnect stress

US10276534B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10276534-B2
Application numberUS-201715671955-A
CountryUS
Kind codeB2
Filing dateAug 8, 2017
Priority dateAug 30, 2016
Publication dateApr 30, 2019
Grant dateApr 30, 2019

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

First claim

Opening claim text (preview).

What is claimed is: 1. An interposer comprising: a matrix of contacts arranged in rows and columns, wherein the matrix of contacts comprise: a plurality of first contacts each comprising a major axis and a minor axis, wherein a surface area of each of the plurality of first contacts decreases radially away from a center of the interposer; and a plurality of second contacts each comprising diameter axes, wherein the major axis of the plurality of first contacts are aligned with a direction of expansion of the interposer. 2. The interposer of claim 1 , wherein the plurality of first contacts are located within a power/ground region of the interposer and the plurality of second contacts are located within an input/output region of the interposer. 3. The interposer of claim 1 , wherein the plurality of first contacts are located within a quintain of the interposer and the plurality of second contacts are located within an perimeter region of the interposer that complexly surrounds the quintain. 4. The interposer of claim 1 , wherein the plurality of first contacts comprise a diagonal contact nearest the interposer center. 5. The interposer of claim 4 , wherein the first contacts within the same row as the diagonal contact are rotated relative to the diagonal contact. 6. The interposer of claim 4 , wherein the first contacts within the same column as the diagonal contact are rotated relative to the diagonal contact. 7. The interposer of claim 4 , wherein the first contacts within the same row as the diagonal contact have aspect ratios and wherein the first contacts within the same column as the diagonal contact have different aspect ratios. 8. A processing device comprising: a matrix of contacts arranged in rows and columns, wherein the matrix of contacts comprise: a plurality of first contacts each comprising a major axis and a minor axis, wherein a surface area of each of the plurality of first contacts decreases radially away from a center of the processing device; and a plurality of second contacts each comprising diameter axes, wherein the major axis of the plurality of first contacts are aligned with a direction of expansion of the processing device. 9. The processing device of claim 8 , wherein the plurality of first contacts are located within a power/ground region of the processing device and the plurality of second contacts are located within an input/output region of the processing device. 10. The processing device of claim 8 , wherein the plurality of first contacts are located within a quintain of the processing device and the plurality of second contacts are located within an perimeter region of the processing device that complexly surrounds the quintain. 11. The processing device of claim 8 , wherein the plurality of first contacts comprise a diagonal contact nearest the processing device center. 12. The processing device of claim 11 , wherein the first contacts within the same row as the diagonal contact are rotated relative to the diagonal contact. 13. The processing device of claim 11 , wherein the first contacts within the same column as the diagonal contact are rotated relative to the diagonal contact. 14. The processing device of claim 11 , wherein the first contacts within the same row as the diagonal contact have aspect ratios and wherein the first contacts within the same column as the diagonal contact have different aspect ratios.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • changes in dispositions · CPC title

  • Top-view layouts, e.g. mirror arrays · CPC title

  • Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

  • Layouts of interconnections · CPC title

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Frequently asked questions

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What does patent US10276534B2 cover?
A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may furt…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W70/65. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 30 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).