Wafer level package solder barrier used as vacuum getter

Patent metadata

Field	Value
Publication number	US-10262913-B2
Application number	US-201815942911-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Jul 11, 2013
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

First claim

What is claimed is:

1. A method of fabricating an electronic device comprising:
providing a first substrate having at least one cavity and a surface surrounding the at least one cavity;
depositing at least one layer of barrier material on the surface of the first substrate;
depositing a solder barrier layer of titanium material on a first portion of the at least one layer of barrier material;
forming a first seal structure on a second portion of the at least one layer of barrier material to form a ring around a perimeter of the at least one cavity, wherein the solder barrier layer of titanium material does not extend into the first seal structure;
activating the solder barrier layer of titanium material in a vacuum environment to function as a getter;
providing a second substrate, the second substrate comprising at least one device attached thereto and a second seal structure, the second seal structure forming a ring around a perimeter of the at least one device;
aligning the first seal structure to the second seal structure, such that the at least one cavity of the first substrate is positioned over the at least one device; and
bonding the first substrate to the second substrate using solder.

2. The method of claim 1 , wherein activating comprises heating the solder barrier layer of titanium material to a temperature in a range of about 200° C. to about 500° C. for a time period in a range of about 10 minutes to about 120 minutes.

3. The method of claim 1 , wherein depositing the solder barrier layer of titanium material includes depositing the solder barrier layer with a thickness of the titanium material being in a range of about 1000 Angstroms to about 10,000 Angstroms.

4. The method of claim 1 , wherein activating the at least one solder barrier layer of titanium material is performed after aligning the first seal structure to the second seal structure.

5. The method of claim 1 , wherein activating the solder barrier layer of titanium material is performed simultaneously with bonding the first substrate to the second substrate.

6. The method of claim 1 , wherein the at least one layer of barrier material comprises titanium-tungsten.

7. The method of claim 6 , wherein the solder barrier layer of titanium material is more porous than the at least one layer of barrier material.

8. The method of claim 7 , wherein the solder barrier layer of titanium material is deposited such that it overlaps a portion of a perimeter of the first seal structure.

Assignees

• Raytheon Co

Inventors

• Gooch Roland W
• Diep Buu Q
• Kennedy Adam M
• Black Stephen H
• Kocian Thomas A

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W76/48

  Fillings including materials for absorbing or reacting with moisture or other undesired substances · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title

• H10W70/66

  Conductive materials thereof · CPC title