Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10256348-B2
Application number	US-201815903097-A
Country	US
Kind code	B2
Filing date	Feb 23, 2018
Priority date	Jan 20, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer;
forming a first insulating layer over the oxide semiconductor layer;
forming a second insulating layer by etching the first insulating layer so that a first part of the oxide semiconductor layer is exposed;
forming a first conductive layer over the first part of the oxide semiconductor layer and the second insulating layer;

forming a second conductive layer by etching the first conductive layer so that part of the first part of the oxide semiconductor layer is exposed, wherein the second conductive layer is along and in contact with a side surface of the second insulating layer;
removing the second insulating layer;
etching the oxide semiconductor layer with the second conductive layer as a mask;
forming a third insulating layer over the oxide semiconductor layer and the second conductive layer after etching the oxide semiconductor layer;
forming a groove in the third insulating layer so that a region of the second conductive layer is exposed;
forming a source electrode layer and a drain electrode layer by removing the region of the second conductive layer; and
forming an oxide layer, a gate insulating layer over the oxide layer and a gate electrode layer over the gate insulating layer in the groove.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese.

3. The method for manufacturing a semiconductor device according to claim 1 ,
wherein a bottom surface of the oxide semiconductor layer is located at a higher level than a bottom surface of the gate electrode layer in a cross section in a channel width direction so that part of a side surface of the oxide semiconductor layer faces the gate electrode layer.

4. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of:
removing part of the second conductive layer before etching the oxide semiconductor layer with the second conductive layer as the mask.

5. The method for manufacturing a semiconductor device according to claim 1 ,
wherein the oxide layer contains at least one metal element contained in the oxide semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer and the oxide layer each comprise indium, gallium and zinc.

7. The method for manufacturing a semiconductor device according to claim 1 , further comprises the step of:
forming a fourth insulating layer over the third insulating layer,
wherein the fourth insulating layer comprises an aluminum oxide.

8. The method for manufacturing a semiconductor device according to claim 7 ,
wherein the fourth insulating layer is in contact with the third insulating layer, the oxide layer, the gate insulating layer and the gate electrode layer.

9. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first oxide layer;
forming an oxide semiconductor layer over and in contact with the first oxide layer;
forming a first insulating layer over the oxide semiconductor layer;
forming a second insulating layer by etching the first insulating layer so that a first part of the oxide semiconductor layer is exposed;
forming a first conductive layer over the first part of the oxide semiconductor layer and the second insulating layer;
forming a second conductive layer by etching the first conductive layer so that part of the first part of the oxide semiconductor layer is exposed, wherein the second conductive layer is along and in contact with a side surface of the second insulating layer;
removing the second insulating layer;
etching the first oxide layer and the oxide semiconductor layer with the second conductive layer as a mask;
forming a third insulating layer over the first oxide layer, the oxide semiconductor layer and the second conductive layer after etching the oxide semiconductor layer and the first oxide layer;
forming a groove in the third insulating layer so that part of the second conductive layer is exposed;
forming a source electrode layer and a drain electrode layer by removing the part of the second conductive layer; and
forming a second oxide layer in contact with the oxide semiconductor layer, a gate insulating layer over the second oxide layer and a gate electrode layer over the gate insulating layer in the groove.

10. The method for manufacturing a semiconductor device according to claim 9 , wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese.

11. The method for manufacturing a semiconductor device according to claim 9 ,
wherein a bottom surface of the oxide semiconductor layer is located at a higher level than a bottom surface of the gate electrode layer in a cross section in a channel width direction so that part of a side surface of the oxide semiconductor layer faces the gate electrode layer.

12. The method for manufacturing a semiconductor device according to claim 9 , further comprising the step of:
removing part of the second conductive layer before etching the oxide semiconductor layer with the second conductive layer as the mask.

13. The method for manufacturing a semiconductor device according to claim 9 ,
wherein the first oxide layer and the second oxide layer each contain at least one metal element contained in the oxide semiconductor layer.

14. The method for manufacturing a semiconductor device according to claim 9 ,
wherein the first oxide layer, the oxide semiconductor layer and the second oxide layer each comprise indium, gallium and zinc.

15. The method for manufacturing a semiconductor device according to claim 9 , further comprises the step of:
forming a fourth insulating layer over the third insulating layer,
wherein the fourth insulating layer comprises an aluminum oxide.

16. The method for manufacturing a semiconductor device according to claim 15 ,
wherein the fourth insulating layer is in contact with the third insulating layer, the second oxide layer, the gate insulating layer and the gate electrode layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Endo Yuta
• Suzawa Hideomi
• Hanaoka Kazuya
• Sasagawa Shinya
• Okamoto Satoru

Classifications

• H01L29/78696 Primary

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic

• H01L2029/42388

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/4908

  Electricity · mapped topic