Oxide semiconductor thin film transistor with reduced impurity diffusion

Patent metadata

Field	Value
Publication number	US-9455349-B2
Application number	US-201414518259-A
Country	US
Kind code	B2
Filing date	Oct 20, 2014
Priority date	Oct 22, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first electrode;
a second electrode over the first electrode;
a first insulating layer in contact with side surfaces of the first electrode and the second electrode;
a second insulating layer in contact with a top surface of the first insulating layer and part of a top surface of the second electrode, the second insulating layer having an opening in a region overlapping with the second electrode;
a third insulating layer over the second electrode and the second insulating layer, wherein the third insulating layer is in contact with the second electrode through the opening of the second insulating layer;
an oxide semiconductor layer overlapping with the first electrode and the second electrode with the third insulating layer sandwiched between the second electrode and the oxide semiconductor layer;
a fourth insulating layer over the oxide semiconductor layer; and
a third electrode over the oxide semiconductor layer with the fourth insulating layer therebetween,
wherein the third electrode overlaps with the opening of the second insulating layer at least partly.

2. The semiconductor device according to claim 1 , wherein each of the first insulating layer and the third insulating layer comprises aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, or silicon oxide.

3. The semiconductor device according to claim 1 , wherein the first electrode comprises aluminum, chromium, titanium, copper, molybdenum, or tungsten.

4. The semiconductor device according to claim 1 ,
wherein the second insulating layer comprises aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

5. The semiconductor device according to claim 1 , wherein the second electrode comprises indium tin oxide, indium tin oxide containing silicon, phosphorus, boron, nitrogen, or carbon, or indium gallium zinc oxide containing silicon, phosphorus, boron, nitrogen, or carbon.

6. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer includes stacked layers including a first oxide semiconductor layer and a second oxide semiconductor layer.

7. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer includes stacked layers in which a second oxide semiconductor layer is sandwiched between a first oxide semiconductor layer and a third oxide semiconductor layer, and
wherein an electron affinity of the second oxide semiconductor layer is larger than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

8. The semiconductor device according to claim 1 , further comprising a source electrode and a drain electrode in contact with the oxide semiconductor layer.

9. The semiconductor device according to claim 1 ,
wherein the third electrode functions as a gate electrode.

10. A semiconductor device comprising:
a first electrode;
a first insulating layer;
a second insulating layer;
a third insulating layer; and
an oxide semiconductor layer,
wherein the first insulating layer is adjacent to a side surface of the first electrode,
wherein the second insulating layer covers the first insulating layer and is in contact with at least part of a surface of the first electrode,
wherein the second insulating layer includes an opening in a region overlapping with the first electrode,
wherein the third insulating layer is over the first electrode and the second insulating layer, and is in contact with the first electrode through the opening of the second insulating layer, and
wherein the first electrode overlaps with the oxide semiconductor layer with the third insulating layer sandwiched between the first electrode and the oxide semiconductor layer.

11. The semiconductor device according to claim 10 ,
wherein the second insulating layer comprises aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

12. The semiconductor device according to claim 10 , wherein the second insulating layer comprises aluminum oxide.

13. The semiconductor device according to claim 10 , wherein the surface of the first electrode comprises indium tin oxide, indium tin oxide containing silicon, phosphorus, boron, nitrogen, or carbon, or indium gallium zinc oxide containing silicon, phosphorus, boron, nitrogen, or carbon.

14. The semiconductor device according to claim 10 , wherein the surface of the first electrode comprises indium gallium zinc oxide containing nitrogen.

15. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor layer includes stacked layers including a first oxide semiconductor layer and a second oxide semiconductor layer.

16. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor layer includes stacked layers in which a second oxide semiconductor layer is sandwiched between a first oxide semiconductor layer and a third oxide semiconductor layer, and
wherein an electron affinity of the second oxide semiconductor layer is larger than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

17. A semiconductor device comprising:
a first gate electrode;
a second gate electrode;
a first gate insulating layer;
a second gate insulating layer;
an oxide semiconductor layer;
a source electrode;
a drain electrode;
a first insulating layer; and
a second insulating layer,
wherein the oxide semiconductor layer is sandwiched between the first gate insulating layer and the second gate insulating layer,
wherein the first gate insulating layer, the oxide semiconductor layer, and the second gate insulating layer are sandwiched between the first gate electrode and the second gate electrode,
wherein the source electrode and the drain electrode are in contact with the oxide semiconductor layer,
wherein the first insulating layer is adjacent to a side surface of the second gate electrode,
wherein the second insulating layer covers the first insulating layer and is in contact with at least part of a surface of the second gate electrode,
wherein the second insulating layer includes an opening in a region overlapping with the second gate electrode, and
wherein the first gate insulating layer is in contact with the second gate electrode through the opening of the second insulating layer.

18. The semiconductor device according to claim 17 ,
wherein the second insulating layer comprises aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

19. The semiconductor device according to claim 17 , wherein the second insulating layer comprises aluminum oxide.

20. The semiconductor device according to claim 17 ,
wherein the surface of the second gate electrode comprises indium tin oxide, indium tin oxide containing silicon, phosphorus, boron, nitrogen, or carbon, or indium gallium zinc oxide containing silicon, phosphorus, boron, nitrogen, or carbon.

21. The semiconductor device according to claim 17 , wherein t

Assignees

• Semiconductor Energy Lab

Inventors

• Suzawa Hideomi
• Tanaka Tetsuhiro
• Sato Yuhei
• Tezuka Sachiaki
• Yamazaki Shunpei

Classifications

• H10D30/6736

  characterised by the shape of gate insulators · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title