Semiconductor device with oxide semiconductor layer

Patent metadata

Field	Value
Publication number	US-9543445-B2
Application number	US-201514666761-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	Dec 25, 2009
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈ r /d is greater than or equal to 0.08 (nm −1 ) and less than or equal to 7.9 (nm −1 ) when the relative permittivity of a material used for the gate insulating layer is ∈ r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an oxide semiconductor layer;
a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;
a first insulating layer over the source electrode and the drain electrode;
a gate insulating layer over the oxide semiconductor layer; and
a gate electrode over the gate insulating layer,
wherein the gate insulating layer is located between a side surface of the first insulating layer and the gate electrode.

2. The semiconductor device according to claim 1 ,
wherein the gate insulating layer is in contact with the side surface of the first insulating layer.

3. The semiconductor device according to claim 1 ,
wherein the first insulating layer is divided into a first region and a second region, and
wherein the first region and the second region are provided on the source electrode and the drain electrode, respectively.

4. The semiconductor device according to claim 1 ,
wherein the first insulating layer is divided into a first region and a second region,
wherein the first region and a first portion of the gate insulating layer are provided between the source electrode and the gate electrode, and
wherein the second region and a second portion of the gate insulating layer are provided between the drain electrode and the gate electrode.

5. The semiconductor device according to claim 1 , further comprising a second insulating layer over the first insulating layer, the gate insulating layer and the gate electrode,
wherein the second insulating layer comprises aluminum oxide.

6. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer includes a crystal region, and
wherein a c-axis of the crystal region is aligned in a direction within ±10° from a perpendicular direction to a surface of the oxide semiconductor layer.

7. The semiconductor device according to claim 1 ,
wherein a thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 50 nm,
wherein the gate insulating layer satisfies a relation where ∈ r /d is greater than or equal to 0.08 (nm −1 ) and less than or equal to 7.9 (nm −1 ) when a relative permittivity of a material used for the gate insulating layer is ∈ r and a thickness of the gate insulating layer is d, and
wherein a distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

8. The semiconductor device according to claim 1 ,
wherein each side surface of the source electrode and the drain electrode has an oxide region.

9. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer on the first oxide semiconductor layer;
a source electrode and a drain electrode electrically connected to the second oxide semiconductor layer;
a first insulating layer over the source electrode and the drain electrode;
a gate insulating layer over the second oxide semiconductor layer; and
a gate electrode over the gate insulating layer,
wherein the gate insulating layer is located between a side surface of the first insulating layer and the gate electrode.

10. The semiconductor device according to claim 9 ,
wherein the gate insulating layer is in contact with the side surface of the first insulating layer.

11. The semiconductor device according to claim 9 ,
wherein the first insulating layer is divided into a first region and a second region, and
wherein the first region and the second region are provided on the source electrode and the drain electrode, respectively.

12. The semiconductor device according to claim 9 ,
wherein the first insulating layer is divided into a first region and a second region,
wherein the first region and a first portion of the gate insulating layer are provided between the source electrode and the gate electrode, and
wherein the second region and a second portion of the gate insulating layer are provided between the drain electrode and the gate electrode.

13. The semiconductor device according to claim 9 , further comprising a second insulating layer over the first insulating layer, the gate insulating layer and the gate electrode,
wherein the second insulating layer comprises aluminum oxide.

14. The semiconductor device according to claim 9 ,
wherein the second oxide semiconductor layer include a crystal region, and
wherein a c-axis of the crystal region is aligned in a direction within ±10° from a perpendicular direction to a surface of the second oxide semiconductor layer.

15. The semiconductor device according to claim 9 ,
wherein the second oxide semiconductor layer includes a crystal region, and
wherein the crystal region includes a layer containing In and a layer containing Ga or Zn which are stacked in a c-axis direction of the crystal region.

16. The semiconductor device according to claim 9 ,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer have a same crystal structure.

17. The semiconductor device according to claim 9 ,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise a material including the same main component.

18. The semiconductor device according to claim 9 ,
wherein the semiconductor device is provided over a surface having an arithmetic mean deviation of 1 nm or less.

19. The semiconductor device according to claim 9 ,
wherein a sum of a thickness of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 50 nm,
wherein the gate insulating layer satisfies a relation where ∈ r /d is greater than or equal to 0.08 (nm −1 ) and less than or equal to 7.9 (nm −1 ) when a relative permittivity of a material used for the gate insulating layer is ∈ r and a thickness of the gate insulating layer is d, and
wherein a distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

20. The semiconductor device according to claim 9 ,
wherein each side surface of the source electrode and the drain electrode has an oxide region.

Assignees

• Semiconductor Energy Lab
• Semiconductor Energy Laborartory Co Ltd

Inventors

• Yamazaki Shunpei
• Godo Hiromichi
• Kawae Daisuke

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H01L29/42384

  Electricity · mapped topic

• H01L29/66477

  Electricity · mapped topic