Transistor, semiconductor device, and electronic device

Patent metadata

Field	Value
Publication number	US-2016233340-A1
Application number	US-201615017831-A
Country	US
Kind code	A1
Filing date	Feb 8, 2016
Priority date	Feb 9, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.

First claim

What is claimed is:

1 . A transistor comprising:
a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer; a first electrode, a second electrode, and a third electrode; and a first insulating layer and a second insulating layer, wherein the first oxide semiconductor layer has an island shape and comprises a first region, a second region, and a third region, wherein the third region is between the first region and the second region, wherein the first electrode is over the first region, wherein the second electrode is over the second region, wherein the first insulating layer is over the first electrode and the second electrode with the second oxide semiconductor layer therebetween, wherein the second oxide semiconductor layer comprises a first opening, wherein the first insulating layer comprises a second opening, wherein the first opening and the second opening each overlap with the third region, wherein the third electrode is over the third region with the third oxide semiconductor layer and the second insulating layer therebetween, wherein the second oxide semiconductor layer covers a first side surface, a second side surface, the first region, and the second region in the first oxide semiconductor layer, and wherein the third oxide semiconductor layer covers third side surfaces and the third region in the first oxide semiconductor layer.

2 . The transistor according to claim 1 ,
wherein the first region includes the first side surface, wherein the second region includes the second side surface, and wherein the third region includes the third side surfaces.

3 . The transistor according to claim 1 , wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a layered crystal structure substantially parallel to the first side surface, the second side surface, and the third side surfaces of the first oxide semiconductor layer.

4 . The transistor according to claim 1 , wherein side surfaces of the third electrode are surrounded by the first insulating layer.

5 . The transistor according to claim 1 , wherein the second oxide semiconductor layer is in contact with the first side surface and the second side surface of the first oxide semiconductor layer.

6 . The transistor according to claim 1 , wherein the third oxide semiconductor layer is in contact with the third side surfaces of the first oxide semiconductor layer.

7 . The transistor according to claim 1 , wherein a channel is formed in the third region.

8 . The transistor according to claim 1 , wherein the first oxide semiconductor layer comprises at least one of In and Zn.

9 . The transistor according to claim 1 , wherein the second oxide semiconductor layer and the third oxide semiconductor layer comprise at least one of metal elements contained in the first oxide semiconductor layer.

10 . A semiconductor device comprising:
the transistor according to claim 1 ; and a capacitor or a resistor.

11 . An electronic device comprising:
the semiconductor device according to claim 10 ; and at least one of an antenna, a battery, an operation switch, a microphone, and a speaker.

12 . An electronic device comprising:
the transistor according to claim 1 ; and at least one of an antenna, a battery, an operation switch, a microphone, and a speaker.

13 . A transistor comprising:
a first oxide semiconductor layer; a first electrode and a second electrode over the first oxide semiconductor layer; a second oxide semiconductor layer over the first electrode and the second electrode, the second oxide semiconductor layer having a first opening; a first insulating layer over the second oxide semiconductor layer, the first insulating layer having a second opening; a third oxide semiconductor layer in the first opening and the second opening; a second insulating layer over the third oxide semiconductor layer; and a third electrode over the third oxide semiconductor layer, wherein the second oxide semiconductor layer covers first side surfaces of the first oxide semiconductor layer crossing a channel length direction of the transistor, and wherein the third oxide semiconductor layer covers second side surfaces of the first oxide semiconductor layer crossing a channel width direction of the transistor.

14 . The transistor according to claim 13 ,
wherein the first opening overlaps with the second opening, and wherein the third oxide semiconductor layer is in contact with a portion of the first oxide semiconductor layer in the first opening and the second opening.

15 . The transistor according to claim 13 , wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a layered crystal structure substantially parallel to the first side surfaces and the second side surfaces of the first oxide semiconductor layer.

16 . The transistor according to claim 13 , wherein side surfaces of the third electrode are surrounded by the first insulating layer.

17 . The transistor according to claim 13 , wherein the second oxide semiconductor layer is in contact with the first side surfaces.

18 . The transistor according to claim 13 , wherein the third oxide semiconductor layer is in contact with the second side surfaces.

19 . The transistor according to a claim 13 , wherein a channel is formed in the first oxide semiconductor layer, and
wherein the channel overlaps with the first opening and the second opening.

20 . The transistor according to claim 13 , wherein the first oxide semiconductor layer comprises at least one of In and Zn.

21 . The transistor according to claim 13 , wherein the second oxide semiconductor layer and the third oxide semiconductor layer comprise at least one of metal elements contained in the first oxide semiconductor layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Shimomura Akihisa
• Okamoto Satoru
• Okazaki Yutaka
• Asami Yoshinobu
• Honda Hiroaki
• Tsurume Takuya

Classifications

• H10P32/17

  characterised by the semiconductor material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title