Display device

Patent metadata

Field	Value
Publication number	US-9842861-B2
Application number	US-201615391938-A
Country	US
Kind code	B2
Filing date	Dec 28, 2016
Priority date	Sep 29, 2006
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a ninth transistor,
wherein one of a source and a drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the first transistor is directly connected to a second wiring,
wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor,
wherein a gate of the second transistor is directly connected to a third wiring,
wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring,
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor,
wherein a gate of the fourth transistor is directly connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring,
wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor,
wherein a gate of the fifth transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring,
wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor,
wherein a gate of the sixth transistor is directly connected to the sixth wiring,
wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring,
wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor,
wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring,
wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor,
wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring,
wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and
wherein a gate of the ninth transistor is directly connected to the seventh wiring.

2. The semiconductor device according to claim 1 , further comprising a tenth transistor,
wherein one of a source and a drain of the tenth transistor is directly connected to the fourth wiring, and
wherein the other of the source and the drain of the tenth transistor is directly connected to the second wiring.

3. The semiconductor device according to claim 2 ,
wherein a gate of the tenth transistor is electrically connected to the seventh wiring.

4. The semiconductor device according to claim 3 ,
wherein the gate of the tenth transistor is directly connected to the seventh wiring.

5. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a ninth transistor,
wherein one of a source and a drain of the first transistor is directly connected to a first signal line,
wherein the other of the source and the drain of the first transistor is directly connected to a second signal line,
wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor,
wherein a gate of the second transistor is directly connected to a third signal line,
wherein one of a source and a drain of the third transistor is directly connected to a power supply line,
wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor,
wherein a gate of the fourth transistor is directly connected to a fourth signal line,
wherein one of a source and a drain of the fifth transistor is directly connected to the power supply line,
wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor,
wherein a gate of the fifth transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is directly connected to a fifth signal line,
wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor,
wherein a gate of the sixth transistor is directly connected to the fifth signal line,
wherein one of a source and a drain of the seventh transistor is directly connected to the fifth signal line,
wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor,
wherein one of a source and a drain of the eighth transistor is directly connected to a sixth signal line,
wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor,
wherein one of a source and a drain of the ninth transistor is directly connected to the sixth signal line,
wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and
wherein a gate of the ninth transistor is directly connected to the sixth signal line.

6. The semiconductor device according to claim 5 , further comprising a tenth transistor,
wherein one of a source and a drain of the tenth transistor is directly connected to the power supply line, and
wherein the other of the source and the drain of the tenth transistor is directly connected to the second signal line.

7. The semiconductor device according to claim 6 ,
wherein a gate of the tenth transistor is electrically connected to the sixth signal line.

8. The semiconductor device according to claim 7 ,
wherein the gate of the tenth transistor is directly connected to the sixth signal line.

9. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor;
a ninth transistor; and
a tenth transistor,
wherein one of a source and a drain of the first transistor is directly connected to a first signal line,
wherein the other of the source and the drain of the first transistor is directly connected to a second signal line,
wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor,
wherein a gate of the second transistor is directly connected to a third signal line,
wherein one of a source and a drain of the third transistor is directly connected to a power supply line,
wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of th

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi
• Miyake Hiroyuki

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title

• G09G2310/0248

  Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

• G09G2320/0666

  for control of colour parameters, e.g. colour temperature · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title