Pulse output circuit, shift register, and display device

Patent metadata

Field	Value
Publication number	US-9543039-B2
Application number	US-201514831939-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	May 21, 2010
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

First claim

The invention claimed is:

1. A display device comprising:
a pixel portion provided on a substrate;
a driver circuit provided on the substrate,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor,
wherein the gate of the first transistor is arranged so that at least a first signal is input,
wherein the gate of the second transistor is arranged so that at least a second signal is input,
wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and
wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion.

2. A display device comprising:
a pixel portion provided on a substrate;
a driver circuit provided on the substrate,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor,
wherein the gate of the first transistor is arranged so that at least a first signal is input,
wherein the gate of the second transistor is arranged so that at least a second signal is input,
wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and
wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion.

3. The display device according to claim 2 , wherein the oxide semiconductor layer comprises a region whose carrier concentration is less than 1×10 11 /cm 3 .

4. The display device according to claim 3 , wherein an off-state current per micrometer of a channel width of at least one of the first transistor to the fifth transistor is 1×10 −20 A.

5. The display device according to claim 1 , wherein an off-state current per micrometer of a channel width of at least one of the first transistor to the fifth transistor is 1×10 −20 A.

6. The display device according to claim 2 , wherein an off-state current per micrometer of a channel width of at least one of the first transistor to the fifth transistor is 1×10 −20 A.

7. The display device according to claim 1 , wherein the driver circuit is a scan line driver circuit.

8. An electronic device comprising:
the display device according to claim 1 ; and
an acceleration sensor, a housing, an optical sensor, a speaker, or an operation button.

9. A shift register comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein each of the first transistor to the fifth transistor is an n-channel transistor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein a gate of the first transistor is directly connected to a gate of the third transistor,
wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor,
wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor,
wherein the gate of the first transistor is arranged so that at least a first signal is input,
wherein the gate of the second transistor is arranged so that at least a second signal is input, and
wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied.

10. A shift register comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein each of the first transistor to the fifth transistor is an n-channel transistor,
wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein a gate of the first transistor is directly connected to a gate of the third transistor,
wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor,
wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor,
wherein the gate of the first transistor is arranged so that at least a first signal is input,
wherein the gate of the second transistor is arranged so that at least a second signal is input, and
wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied.

11. The shift register according to claim 10 , wherein the oxide semiconductor layer comprises a region whose carrier concentration is less than 1×10 11 /cm 3 .

12. The shift register according to claim 11 , wherein an off-state current per micrometer of a channel width of at least one of the first transistor to the fifth transistor is 1×10 −20 A.

13. A display device

Assignees

• Semiconductor Energy Lab

Inventors

• Amano Seiko
• Miyake Hiroyuki

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0871

  with level shifting · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title