Display device

Patent metadata

Field	Value
Publication number	US-9536903-B2
Application number	US-201414548365-A
Country	US
Kind code	B2
Filing date	Nov 20, 2014
Priority date	Sep 29, 2006
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

First claim

What is claimed is:

1. A liquid crystal display device comprising:
a gate driver circuit formed over a substrate, the gate driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a seventh transistor; and

a pixel formed over the substrate, the pixel comprising:
an eighth transistor;
a first conductive layer; and
a second conductive layer,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,
wherein a gate of the third transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fourth transistor is electrically connected to a sixth wiring,
whrerein one of a source and a drain of the fifth transistor is electrically connected to a seventh wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to an eighth wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein a gate of the seventh transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the sixth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the seventh transistor,
wherein a first insulating film is over the eighth transistor,
wherein the first conductive layer is over the first insulating film,
wherein a second insulating film is over the first conductive layer,
wherein the second conductive layer is over the second insulating film,
wherein a liquid crystal is over the second conductive layer,
wherein the second insulating film comprises a part which is sandwiched by the first conductive layer and the second conductive layer,
wherein a gate of the eighth transistor is electrically connected to the second wiring,
wherein the first insulating film comprises a first contact hole,
wherein the second insulating film comprises a second contact hole, and
wherein the second conductive layer is electrically connected to one of a source and a drain of the eighth transistor through the second contact hole and the first contact hole.

2. The liquid crystal display device according to claim 1 ,
wherein a first clock signal is input to the first wiring, and
wherein a second clock signal is input to the fifth wiring.

3. The liquid crystal display device according to claim 1 ,
wherein the eighth transistor has a bottom-gate structure.

4. The liquid crystal display device according to claim 1 ,
wherein the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor.

5. A liquid crystal display device comprising:
a gate driver circuit formed over a substrate, the gate driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a seventh transistor; and

a pixel formed over the substrate, the pixel comprising:
an eighth transistor;
a first conductive layer; and
a second conductive layer,

wherein one of a source and a drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the first transistor is directly connected to a second wiring,
wherein one of a source and a drain of the second transistor is directly connected to a third wiring,
wherein the other of the source and the drain of the second transistor is directly connected to the second wiring,
wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is directly connected to a gate of the second transistor,
wherein a gate of the third transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fourth transistor is directly connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the second transistor,
wherein a gate of the fourth transistor is directly connected to a sixth wiring,
whrerein one of a source and a drain of the fifth transistor is directly connected to a seventh wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein a gate of the fifth transistor is directly connected to an eighth wiring,
wherein one of a source and a drain of the sixth transistor is directly connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is directly connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the sixth transistor is directly connected to the gate of the second transistor,
wherein one of a source and a drain of the seventh transistor is directly connected to the third wiring,
wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the second transistor,
wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the fifth transistor,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor,
wherein the ratio of the channel wid

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi
• Miyake Hiroyuki

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0248

  Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

• G09G2320/0646

  Modulation of illumination source brightness and image signal correlated to each other · CPC title