Systems and methods for wafer alignment

Patent metadata

Field	Value
Publication number	US-10242901-B2
Application number	US-201816046201-A
Country	US
Kind code	B2
Filing date	Jul 26, 2018
Priority date	Jun 1, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

First claim

We claim:

1. A system for aligning a wafer, the system comprising a controller configured to:
perform a coarse alignment procedure by:
estimating a misalignment of the wafer based on a comparison of a plurality of electrical features on the wafer and a template, and
adjusting a position of the wafer based on the estimated misalignment; and

perform, after performing the coarse alignment procedure, a fine alignment procedure by:
determining a center location of individual electrical features of the plurality of electrical features on the wafer,
averaging the center locations of the individual electrical features together to obtain an average center location of the plurality of electrical features
comparing the average center location with a reference location, and
adjusting the position of the wafer based on the comparison of the average center location with the reference location if the average center location is not within a predetermined distance of the reference location.

2. The system of claim 1 , wherein the controller is configured to perform the coarse alignment procedure by estimating the misalignment of the wafer based on the comparison of the plurality of electrical features on the wafer and the template by receiving imaging data and comparing the imaging data to predetermined imaging data associated with the template.

3. The system of claim 1 , wherein the controller is configured to perform the fine alignment procedure by determining the center location of the individual electrical features by computing an x and y coordinate for the individual electrical features in the plurality of electrical features and computing an average x and y coordinate for the average center location.

4. The system of claim 1 , wherein the controller is configured to perform the fine alignment procedure by determining the center location of the individual electrical features by detecting light intensity reflected from the wafer.

5. A system for aligning a wafer, the system comprising a controller configured to:
determine a center location of individual electrical features of a plurality of electrical features on the wafer;
average the center locations of the individual electrical features together to obtain an average center location of the plurality of electrical features;
compare the average center location with a reference location; and
adjust a position of the wafer based on the comparison if the average center location is not within a predetermined distance of the reference location.

6. The system of claim 5 , wherein the controller is further configured to:
compare the plurality of electrical features to a template;
estimate misalignment of the wafer based on a comparison of the plurality of electrical features and the template; and
adjust the position of the wafer based on the estimated misalignment.

7. The system of claim 5 , wherein the controller is configured to determine the center location of the individual electrical features by detecting intensity of light reflected from the plurality of electrical features.

8. The system of claim 5 , wherein the controller is configured to determine the center location of the individual electrical features by determining the center location of the individual electrical features based on shape or image pattern recognition.

9. The system of claim 5 , wherein the reference location is a center of a camera view field or a reference point associated with the wafer.

10. The system of claim 5 , wherein the controller is configured to adjust the position of the wafer by moving a substrate support configured to hold the wafer.

11. The system of claim 5 , wherein the controller is configured to average the center locations by computing a mean, median, or weighted average.

12. A system for aligning a wafer, the system comprising a controller configured to:
determine center locations of individual electrical features of a plurality of electrical features on the wafer;
average the center locations of the individual electrical features together to obtain an average center location of the plurality of electrical features;
compare the average center location with a reference location; and
adjust a position of the wafer based on the comparison if the average center location is not within a prescribed distance of the reference location.

13. The system of claim 12 , wherein the controller is further configured to:
before determining the center locations of the individual electrical features, receive digital imaging data from an image sensor for at least a portion of the wafer;
determine that the portion of the wafer matches a template;
perform a coarse alignment procedure by estimating misalignment of the wafer based on a comparison of the portion of the wafer and the template; and
adjust the position of the wafer based on the estimated misalignment.

14. The system of claim 12 , the system further comprising an electrical motor configured to move the wafer.

15. The system of claim 12 , wherein the reference location is a reference point associated with an electrical feature of the wafer.

16. A system for aligning a wafer, the system comprising:
means for determining an offset of an average center location of a plurality of electrical features fabricated on the wafer with a reference center location of an alignment template associated with the wafer, wherein the average center location of the plurality of electrical features is based on center locations of the individual electrical features in the plurality of electrical features; and
means for aligning the wafer to a processing tool based on the determined offset.

17. The system of claim 16 , further comprising:
means for performing, before determining the offset of the average center location of the plurality of electrical features, a coarse alignment procedure by comparing the plurality of electrical features to a template;
means for estimating misalignment of the wafer based on a comparison of the plurality of electrical features and the template; and
means for adjusting a position of the wafer based on the estimated misalignment.

18. The system of claim 16 , wherein the means for determining the offset of the average center location of the individual electrical features comprise:
means for determining the average center location of the plurality of electrical features based on shape or image pattern recognition or detecting intensity of light reflected from the plurality of electrical features.

Assignees

• Micron Technology Inc

Inventors

• Chao Yang
• Ypma Keith E
• Strauch Steve J

Classifications

• H10P72/53 Primary

  using optical controlling means · CPC title

• G03F7/70775

  Position control, e.g. interferometers or encoders for determining the stage position · CPC title

• G03F9/7007 Primary

  Alignment other than original with workpiece · CPC title

• G03F7/70633

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

• G01B11/14

  for measuring distance or clearance between spaced objects or spaced apertures (G01B11/26 takes precedence; rangefinders G01C3/00) · CPC title