Systems and methods for wafer alignment

Patent metadata

Field	Value
Publication number	US-10062595-B2
Application number	US-201715657298-A
Country	US
Kind code	B2
Filing date	Jul 24, 2017
Priority date	Jun 1, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

First claim

We claim:

1. A method for aligning a wafer, the method comprising:
performing a coarse alignment procedure by:
estimating a misalignment of the wafer based on a first comparison of a plurality of electrical features on the wafer and a template, and
adjusting a position of the wafer based on the estimated misalignment; and

after performing the coarse alignment procedure, performing a fine alignment procedure by:
determining a center location of individual electrical features of the plurality of electrical features on the wafer,
averaging the center locations of the individual electrical features together to obtain an average center location of the plurality of electrical features
comparing, in a second comparison, the average center location with a reference location, and
adjusting the position of the wafer based on the second comparison if the average center location is not within a predetermined distance of the reference location.

2. The method of claim 1 , wherein estimating misalignment of the wafer based on the comparison of the plurality of electrical features on the wafer and the template further comprises receiving imaging data and comparing the imaging data to predetermined imaging data associated with the template.

3. The method of claim 1 , wherein determining the center location of the individual electrical features further comprises computing an x and y coordinate for the individual electrical features in the plurality of electrical features and computing an average x and y coordinate for the average center location.

4. The method of claim 1 , wherein determining the center location of the individual electrical features further comprises detecting light intensity reflected from the wafer.

5. A method for aligning a wafer, the method comprising:
determining a center location of individual electrical features of a plurality of electrical features on the wafer;
averaging the center locations of the individual electrical features together to obtain an average center location of the plurality of electrical features;
comparing the average center location with a reference location; and
adjusting a position of the wafer based on the comparison if the average center location is not within a predetermined distance of the reference location.

6. The method of claim 5 , the method further comprising:
comparing the plurality of electrical features to a template;
estimating misalignment of the wafer based on a comparison of the plurality of electrical features and the template; and
adjusting the position of the wafer based on the estimated misalignment.

7. The method of claim 5 , wherein determining the center location of the individual electrical features further comprises:
detecting intensity of light reflected from the plurality of electrical features.

8. The method of claim 5 , wherein determining the center location of the individual electrical features further comprises:
determining the center location of the individual electrical features based on shape or image pattern recognition.

9. The method of claim 5 , wherein the reference location is a center of a camera view field or a reference point associated with the wafer.

10. The method of claim 5 , wherein adjusting the position of the wafer further comprises moving a substrate support configured to hold the wafer.

11. The method of claim 5 , wherein averaging the center locations comprises computing a mean, median, or weighted average.

12. A system for aligning a wafer, the system comprising:
an image sensor;
an illumination source;
a substrate support configured to hold the wafer;
a controller configured to:
determine center locations of individual electrical features of a plurality of electrical features on a wafer;
average the center locations of the individual electrical features together to obtain an average center location of the plurality of electrical features;
compare the average center location with a reference location; and
adjust a position of the wafer based on the comparison if the average center location is not within a prescribed distance of the reference location.

13. The system of claim 12 , wherein the controller is further configured to:
before determining the center locations of the individual electrical features, receive digital imaging data from the image sensor for at least a portion of the wafer;
determine that the portion of the wafer matches a template;
perform a coarse alignment procedure by estimating misalignment of the wafer based on a comparison of the portion of the wafer and the template; and
adjust the position of the wafer based on the estimated misalignment.

14. The system of claim 12 , the system further comprising an electrical motor configured to move the substrate support.

15. The system of claim 12 , the system further comprising a mask or lens.

16. The system of claim 12 , wherein the reference location is a center of a view field of the image sensor or a reference point associated with an electrical feature.

17. A method for aligning a wafer, the method comprising:
determining an offset of an average center location of a plurality of electrical features fabricated on the wafer with a reference center location of an alignment template associated with the wafer, wherein the average center location of the plurality of electrical features is based on center locations of the individual electrical features in the plurality of electrical features; and
aligning the wafer to a processing tool based on the determined offset.

18. The method of claim 17 , the method further comprising:
before determining the offset of the average center location of the plurality of electrical features, performing a coarse alignment procedure by comparing the plurality of electrical features to a template;
estimating misalignment of the wafer based on a comparison of the plurality of electrical features and the template; and
adjusting a position of the wafer based on the estimated misalignment.

19. The method of claim 17 , wherein determining an offset of an average center location of the individual electrical features further comprises:
determining the average center location of the plurality of electrical features based on shape or image pattern recognition or detecting intensity of light reflected from the plurality of electrical features.

Assignees

• Micron Technology Inc

Inventors

• Chao Yang
• Ypma Keith E
• Strauch Steve J

Classifications

• H10P72/53 Primary

  using optical controlling means · CPC title

• G03F7/70775

  Position control, e.g. interferometers or encoders for determining the stage position · CPC title

• G03F9/7003

  Alignment type or strategy, e.g. leveling, global alignment · CPC title

• B65G2203/041

  Camera · CPC title

• G03F9/7007 Primary

  Alignment other than original with workpiece · CPC title