Nanowire FET including nanowire channel spacers

Patent metadata

Field	Value
Publication number	US-10236362-B2
Application number	US-201615198622-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.

First claim

What is claimed is:

1. A method of forming nanowire channel spacers in a nanowire field effect transistor (FET), the method comprising:
forming a multi-stack semiconductor fin on an upper surface of a semiconductor substrate, the multi-stack semiconductor fin comprising a plurality of vertically stacked semiconductor material layers including plurality of nanowire channel layers, each nanowire channel layer vertically separated from one another by a sacrificial layer;
forming a gate stack on the upper surface of the semiconductor substrate, the gate stack wrapping around the outer surfaces of the multi-stack semiconductor fin;
forming source/drain regions on the upper surface of the semiconductor substrate, the source/drain regions contacting the multi-stack fin and being separated from the gate stack by a void that exposes portions of the sacrificial layers and the nanowire channel layers;
etching the exposed portions of the sacrificial layers to form cavities that release opposing ends of the nanowire channel layers and form stacked nanowire channels; and
filing the cavities with a spacer material that encapsulates the released ends and forms the nanowire channel spacers,
wherein the gate stack and the sacrificial spacers comprise the same dielectric material, and wherein the gate stack includes a gate cap having a first thickness that is greater than a second thickness of the sacrificial spacers.

2. The method of claim 1 , wherein the spacer material comprises a low-dielectric (low-K) material.

3. The method of claim 1 , wherein the nanowire channel spacers are interposed between the source/drain regions and the gate stack.

4. The method of claim 3 , wherein forming the source/drain regions further comprises:
forming sacrificial spacers on sidewalls of the gate stack prior to forming the source/drain regions;
after forming the sacrificial spacers, epitaxially growing the source/drain regions such that the sacrificial spacers are interposed between the source/drain regions and the gate stack; and
selectively etching the sacrificial spacers to form the voids that expose the portions of the sacrificial layers and the nanowire channel layers.

5. The method of claim 4 , wherein the gate stack comprises a first dielectric material and the sacrificial spacers comprises a second dielectric material different from the first dielectric material.

6. The method of claim 1 , wherein the sacrificial layers comprise silicon germanium (SiGe) and the nanowire channel layers comprises silicon (Si).

7. The method of claim 6 , wherein forming the stacked nanowire channels includes performing a selective etching process comprising at least one of a hot standard clean 1 cycle (SC1) wet etch and a hydrochloride (HCl) dry etchant that etches the sacrificial layers while maintaining the nanowire channel layers.

8. The method of claim 1 , wherein filing the cavities with the spacer material further comprises forming the spacer material on remaining portions of the sacrificial material located beneath the gate stack.

9. A method of forming nanowire channel spacers in a nanowire field effect transistor (FET), the method comprising:
forming a first material layer comprising a first semiconductor material on a semiconductor substrate;
forming a second semiconductor layer comprising a second semiconductor material on the first layer;
forming a third semiconductor layer comprising the first semiconductor material on the second layer;
patterning the first, second, and third semiconductor layers to form a multi-layer semiconductor fin including a channel layer portion comprising the second semiconductor material interposed between first and second sacrificial layer portions comprising the first semiconductor material;
forming a sacrificial gate stack that wraps around the exterior surfaces of the multi-layer semiconductor fin, and forming source/drain regions on the substrate so as to define a void between the sacrificial gate stack and the source/drain regions that exposes portions of the sacrificial layer portions and the channel layer portion;
removing the exposed portions of the sacrificial layer portions to form cavities that release ends of the channel layer portion and define a nanowire channel; and
filling the cavities with a spacer material to form the nanowire channel spacers that encapsulate the ends of the channel layer portion,
wherein the sacrificial gate stack and the sacrificial spacers comprise the same dielectric material, and wherein the sacrificial gate stack includes a gate cap having a first thickness that is greater than a second thickness of the sacrificial spacers.

10. The method of claim 9 , wherein filing the cavities with the spacer material further comprises forming the spacer material on remaining portions of the first and second sacrificial layer portions located beneath the sacrificial gate stack.

11. The method of claim 9 , wherein the nanowire channel spacers are interposed between the source/drain regions and the sacrificial gate stack.

12. The method of claim 11 , wherein forming the nanowire channel spacers includes depositing a low-dielectric (low-K) material in the cavities.

13. The method of claim 11 , wherein the sacrificial gate stack comprises a first dielectric material and the sacrificial spacers comprises a second dielectric material different from the first dielectric material.

14. The method of claim 11 , wherein forming the source/drain regions further comprises:
forming sacrificial spacers on sidewalls of the sacrificial gate stack prior to forming the source/drain regions;
after forming the sacrificial spacers, epitaxially growing the source/drain regions from sidewalls of the multi-layer semiconductor fin such that the sacrificial spacers are interposed between the source/drain regions and the sacrificial gate stack; and
selectively etching the sacrificial spacers to form the voids that expose the portions of the sacrificial layers and the channel layer.

15. The method of claim 14 , further comprising replacing the sacrificial gate stack with an electrically conductive gate material such that the electrically conductive gate material covers the channel layer portion and the first and second sacrificial layer portions.

16. The method of claim 9 , wherein the sacrificial layers comprise silicon germanium (SiGe) and the channel layer comprises silicon (Si).

17. The method of claim 16 , wherein defining the nanowire channel includes performing a selective etching process comprising hot standard clean 1 cycle (SC1) wet etching or a hydrochloride (HCl) dry etchant that etches the sacrificial layers while maintaining the channel layer.

Assignees

• IBM

Inventors

• Seo Soon-Cheon

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L29/6653

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic