Thin film transistor of display apparatus
US-2015380567-A1 · Dec 31, 2015 · US
Stacked semiconductor nanowires with tunnel spacers
US8969149B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969149-B2 |
| Application number | US-201313893896-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 14, 2013 |
| Priority date | May 14, 2013 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor structure, said method comprising: providing at least one multilayered stacked semiconductor material structure on a semiconductor substrate and at least one sacrificial gate material structure straddling a portion of the at least one multilayered stacked semiconductor structure, wherein the at least one multilayered stacked semiconductor material structure includes alternating layers of a sacrificial semiconductor materia…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969149B2 cover?
- A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial se…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6706. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).