Technologies for automatic timing calibration in an inter-integrated circuit data bus

Patent metadata

Field	Value
Publication number	US-10229086-B2
Application number	US-201514998310-A
Country	US
Kind code	B2
Filing date	Dec 26, 2015
Priority date	Dec 26, 2015
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Technologies for controlling timing calibration of a dedicated inter-integrated circuit data bus by a primary microcontroller are disclosed. The primary microcontroller performs a data transfer with a secondary integrated circuit using the dedicated inter-integrated circuit data bus, and determines a duration of the data transfer. If the duration is outside of an acceptable range, the primary microcontroller updates one or more data transfer timing parameters so that the duration of future data transfers are closer to the acceptable range.

First claim

The invention claimed is:

1. A system for controlling a timing calibration of a dedicated inter-integrated circuit (IC) data bus, the system comprising:
a microcontroller comprising:
a data transfer timing parameter determination module to acquire one or more data transfer timing parameters comprising at least one of (i) a hold high time period associated with a clock line of the dedicated inter-IC data bus and a hold low time period associated with the clock line or (ii) a current source parameter indicative of an activation of a current source to pull up the clock line;
a data transfer module to perform, using the dedicated inter-IC data bus, a data transfer to a secondary integrated circuit communicatively coupled to the dedicated inter-IC data bus using the one or more data transfer timing parameters; and
a data transfer duration determination module to (i) determine a duration of the data transfer and (ii) update, based on the duration of the data transfer, the one or more data transfer timing parameters, wherein to update the one or more data transfer timing parameters comprises to update, based on the duration of the data transfer, at least one of (i) the hold high time period, (ii) the hold low time period, or (iii) the current source parameter.

2. The system of claim 1 ,
wherein the one or more data transfer timing parameters comprise the hold high time period and the hold low time period, and
wherein to update, based on the duration of the data transfer, the one or more data transfer timing parameters comprises to update, based on the duration of the data transfer, at least one of the hold high time period and the hold low time period.

3. The system of claim 2 , further comprising the dedicated inter-IC data bus and a plurality of secondary ICs, wherein each secondary IC is communicatively coupled to the dedicated inter-IC data bus, and wherein to perform a data transfer comprises to:
send, by the data transfer module and using the dedicated inter-IC data bus, an address to the plurality of secondary ICs, wherein the address indicates a targeted secondary IC,
acknowledge, by the targeted secondary IC and using the dedicated inter-IC data bus, the sent address, and
send, by the data transfer module and using the dedicated inter-IC data bus, data to the targeted secondary IC.

4. The system of claim 3 , wherein the dedicated inter-IC data bus comprises a data line.

5. The system of claim 1 , wherein the one or more data transfer timing parameters comprise the current source parameter, and wherein to update, based on the duration of the data transfer, the one or more data transfer timing parameters comprises to update, based on the duration of the data transfer, the current source parameter.

6. The system of claim 1 , wherein the data transfer comprises a transaction.

7. The system of claim 6 , wherein to perform the data transfer comprises to send a start bit and to send a stop bit, and wherein to determine the duration of the data transfer comprises to determine a duration of the data transfer based on a duration between the start bit and the stop bit.

8. The system of claim 1 ,
wherein the one or more data transfer timing parameters comprise an acceptable range of the duration of the data transfer, the hold high time period, and the hold low time period,
wherein the data transfer timing parameter determination module is further to determine whether the duration of the data transfer is within the acceptable range,
wherein to update the one or more data transfer timing parameters comprises to update, in response to a determination that the duration of the data transfer is not within the acceptable range, at least one of the hold high time period and the hold low time period.

9. The system of claim 1 , wherein the microcontroller is configured to acquire the one or more data transfer timing parameters, perform the data transfer, determine the duration of the data transfer, and update the one or more data transfer timing parameters without instruction from a user of the microcontroller.

10. One or more non-transitory computer-readable media comprising a plurality of instructions stored thereon that, when executed, cause a microcontroller to:
acquire one or more data transfer timing parameters associated with a dedicated inter-integrated circuit (IC) data bus, the one or more parameters comprising at least one of (i) a hold high time period associated with a clock line of the dedicated inter-IC data bus and a hold low time period associated with the clock line or (ii) a current source parameter indicative of an activation of a current source to pull up the clock line;
perform, using the dedicated inter-IC data bus, a data transfer to a secondary integrated circuit communicatively coupled to the dedicated inter-IC data bus using the one or more data transfer timing parameters;
determine a duration of the data transfer; and
update, based on the duration of the data transfer, the one or more data transfer timing parameters, wherein to update the one or more data transfer parameters comprises to update, based on the duration of the data transfer, at least one of (i) the hold high time period, (ii) the hold low time period, or (iii) the current source parameter.

11. The one or more non-transitory computer-readable media of claim 10 , wherein the one or more data transfer timing parameters comprise the hold high time period and the hold low time period, and
wherein to update, based on the duration of the data transfer, the one or more data transfer timing parameters comprises to update, based on the duration of the data transfer, at least one of the hold high time period and the hold low time period.

12. The one or more non-transitory computer-readable media of claim 11 , wherein to perform a data transfer comprises to:
send, by the microcontroller and using the dedicated inter-IC data bus, an address to a plurality of secondary ICs, wherein each secondary IC is communicatively coupled to the dedicated inter-IC data bus, wherein the address indicates a targeted secondary IC;
receive, using the dedicated inter-IC data bus, an acknowledgement of the sent address from the targeted secondary IC; and
send, using the dedicated inter-IC data bus, data to the targeted secondary IC.

13. The one or more non-transitory computer-readable media of claim 10 , wherein the one or more data transfer timing parameters comprise the current source parameter, and wherein to update, based on the duration of the data transfer, the one or more data transfer timing parameters comprises to update, based on the duration of the data transfer, the current source parameter.

14. The one or more non-transitory computer-readable media of claim 10 , wherein the data transfer comprises a transaction.

15. The one or more non-transitory computer-readable media of claim 14 , wherein to perform the data transfer comprises to send a start bit at a start time and to send a stop bit at a stop time, and wherein to determine the duration of the data transfer comprises to determine a duration of the data transfer based on a duration between the start time and the stop time.

16. The one or more non-transitory computer-readable media of claim 10 ,
wherein the one or more data transfer timing parameters comprise an acceptable range of the duration of the data transfer, the hold high time period, and the hold low time period,
wherein the plurality of instructions further cause the microcontroller to determine whether the duration of the data transfer is within the acceptable range, and
wherein to update the one or more data

Assignees

• Intel Corp

Inventors

• Barcohen Yuli
• Kupermann Eli
• Brill Alexander

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/226

  Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format · CPC title