Storage control device and control device for detecting abnormality of signal line

Patent metadata

Field	Value
Publication number	US-9645898-B2
Application number	US-201414313530-A
Country	US
Kind code	B2
Filing date	Jun 24, 2014
Priority date	Jul 9, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A controller module (CM) includes buffers that feed back signals output using respective signal lines used for mutual communication with other CM, and a first detecting unit and a second detecting unit that detect abnormality such that the levels of the signals output using the signal lines do not change from respective specific levels when each level of the fed-back signals does not coincide with an expected level being a level previously determined according to a predetermined timing.

First claim

What is claimed is:

1. A non-transitory computer-readable recording medium storing therein a control program that causes a computer to execute a process comprising:
outputting a signal at a timing before or after reception of a timing signal indicating a predetermined timing, the signal being used for mutual communication with other storage control device; and
detecting abnormality of the signal output being unchanged, the abnormality being detected when a level of a signal fed back through a signal line does not coincide with an expected level, the expected level being determined according to the predetermined timing and whether the signal fed back is output before or after the issue of the timing signal.

2. A control device comprising:
a feedback unit that feeds back a signal output at a timing before or after reception of a timing signal indicating a predetermined timing, the signal being used for mutual communication with other control device; and
a detecting unit that detects abnormality of the signal output being unchanged, the abnormality being detected when a level of the signal fed back by the feedback unit does not coincide with an expected level, the expected level being determined according to the predetermined timing and whether the signal fed back is output before or after the issue of the timing signal.

3. The control device according to claim 2 , wherein
the feedback unit feeds back a clock signal output using a signal line, and
the detecting unit includes a second detecting unit that detects the abnormality of the signal output being unchanged and kept a specific level, when a level of the clock signal fed back by the feedback unit does not coincide with a first level or a second level within a given period of time for ½ cycle of the clock after detection of the first level or the second level, the first level and the second level being the expected levels and different from one another.

4. The control device according to claim 3 , wherein
the second detecting unit includes a third detecting unit that detects abnormality of the signal output when the counted period of time exceeds a specified time, the third detecting unit counting a period of time in which the first level continues when the level of the clock signal does not coincide with the second level after the elapse of the given period of time since the detection of the first level, the third detecting unit detecting clock stretch in the other control device when the counted period of time does not exceed the specified time.

5. The control device according to claim 2 , wherein
the predetermined timing includes a timing indicating start of access for the mutual communication and a timing indicating completion of access for the mutual communication.

Assignees

• Fujitsu Ltd

Inventors

• Kidamura Takashi
• Fujii Kuniaki

Classifications

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• G06F11/1612

  where the redundant component is persistent storage · CPC title

• G06F11/1679

  at clock signal level · CPC title

• G06F11/1637

  using additional compare functionality in one or some but not all of the redundant processing components · CPC title