Methods to send extra information in-band on inter-integrated circuit (I2C) bus

Patent metadata

Field	Value
Publication number	US-9928208-B2
Application number	US-201514700860-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Apr 2, 2014
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

First claim

What is claimed is:

1. A method of data communications on a serial bus, comprising:
communicating with a first device coupled to the serial bus using first signaling transmitted in accordance with an Inter-Integrated Circuit (I2C) protocol; and
communicating with a second device coupled to the serial bus using second signaling that is ignored by a receiver of the first device in accordance with the I2C protocol,
wherein the second signaling includes one or more pulses that have a duration that is less than a maximum duration specified by the I2C protocol for a spike that is to be ignored by the receiver.

2. The method of claim 1 , wherein the one or more pulses in the second signaling have a duration that is less than a minimum duration specified by the I2C protocol for a pulse transmitted on an I2C bus.

3. The method of claim 1 , wherein the one or more pulses in the second signaling are transmitted on a serial clock line (SCL) of the serial bus.

4. The method of claim 1 , wherein the one or more pulses in the second signaling are transmitted on a serial data line (SDA) of the serial bus.

5. The method of claim 1 , wherein the maximum duration specified by the I2C protocol for the spike is 50 nanoseconds.

6. The method of claim 1 , wherein an input filter of the receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds.

7. An apparatus coupled to a serial bus, comprising:
means for communicating with a first device coupled to the serial bus using first signaling transmitted in accordance with an Inter-Integrated Circuit (I2C) protocol; and
means for communicating with a second device coupled to the serial bus using second signaling that is ignored by a receiver of the first device in accordance with the I2C protocol,
wherein the second signaling includes one or more pulses that have a duration that is less than a maximum duration specified by the I2C protocol for a spike that is to be ignored by the receiver.

8. The apparatus of claim 7 , wherein the one or more pulses in the second signaling have a duration that is less than a minimum duration specified by the I2C protocol for a pulse transmitted on an I2C bus.

9. The apparatus of claim 7 , wherein the one or more pulses in the second signaling are transmitted on a serial clock line (SCL) of the serial bus.

10. The apparatus of claim 7 , wherein the one or more pulses in the second signaling are transmitted on a serial data line (SDA) of the serial bus.

11. The apparatus of claim 7 , wherein the maximum duration specified by the I2C protocol for the spike is 50 nanoseconds.

12. The apparatus of claim 7 , wherein an input filter of the receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds.

13. An apparatus configured to be coupled to a serial bus, comprising:
an encoder configured to:
encode first data in first signaling in accordance with Inter-Integrated Circuit (I2C) protocols;
encode second data in second signaling such that the second signaling is ignored by a receiver operating in accordance with the I2C protocols;

a transmitter configured to transmit the first signaling and the second signaling on the serial bus; and
a processing circuit configured to:
communicate with a first device coupled to the serial bus using the first signaling; and
communicate with a second device coupled to the serial bus using the second signaling,

wherein the second signaling includes one or more pulses that have a duration that is less than a maximum duration specified by the I2C protocols for a spike that is to be ignored by the receiver.

14. The apparatus of claim 13 , wherein the one or more pulses in the second signaling have a duration that is less than a minimum duration specified by the I2C protocols for a pulse transmitted on an I2C bus.

15. The apparatus of claim 13 , wherein the one or more pulses in the second signaling are transmitted on a serial clock line (SCL) of the serial bus.

16. The apparatus of claim 13 , wherein the one or more pulses in the second signaling are transmitted on a serial data line (SDA) of the serial bus.

17. The apparatus of claim 13 , wherein the maximum duration specified by the I2C protocols for the spike is 50 nanoseconds.

18. The apparatus of claim 13 , wherein an input filter of the receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds.

19. A processor readable non-transitory storage medium comprising code for:
communicating with a first device coupled to a serial bus using first signaling transmitted in accordance with an Inter-Integrated Circuit (I2C) protocol; and
communicating with a second device coupled to the serial bus using second signaling that is ignored by a receiver of the first device in accordance with the I2C protocol,
wherein the second signaling includes one or more pulses that have a duration that is less than a maximum duration specified by the I2C protocol for a spike that is to be ignored by the receiver.

20. The storage medium of claim 19 , wherein the one or more pulses in the second signaling have a duration that is less than a minimum duration specified by the I2C protocol for a pulse transmitted on an I2C bus.

21. The storage medium of claim 19 , wherein the one or more pulses in the second signaling are transmitted on a serial clock line (SCL) of the serial bus.

22. The storage medium of claim 19 , wherein the one or more pulses in the second signaling are transmitted on a serial data line (SDA) of the serial bus.

23. The storage medium of claim 19 , wherein the maximum duration specified by the I2C protocol for the spike is 50 nanoseconds.

24. The storage medium of claim 19 , wherein an input filter of the receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds.

Assignees

• Qualcomm Inc

Inventors

• Sengoku Shoichiro

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• H04L12/6418

  Hybrid transport · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title