Memory device

Patent metadata

Field	Value
Publication number	US-10224374-B2
Application number	US-201715697388-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Mar 7, 2017
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.

First claim

What is claimed is:

1. A memory device comprising:
a first interconnection extending in a first direction;
a plurality of second interconnections extending in a second direction intersecting the first direction; and
a first resistance change film provided between the first interconnection and the plurality of second interconnections, wherein the first resistance change film comprises:
a first conductive layer having a first conductivity;
a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity;
an insulating layer provided between the second conductive layer and the second interconnection; and
a third conductive layer provided between the insulating layer and the plurality of second interconnections and having the second conductivity higher than first conductivity.

2. The memory device according to claim 1 , wherein
the second conductive layer and the third conductive layer comprise a crystallized metal oxide.

3. The memory device according to claim 2 , wherein
the second conductive layer and the third conductive layer comprise a crystallized titanium oxide or a crystallized tungsten oxide.

4. The memory device according to claim 1 , wherein
the insulating layer comprises a plurality of sections disposed between the respective plurality of second interconnections and the first conductive layer, and isolated from one another.

5. The memory device according to claim 1 , wherein
the second conductive layer and and the third conductive layer extend in the first direction and are continuously provided between the plurality of second interconnections and the first conductive layer.

6. The memory device according to claim 5 , further comprising:
a plurality of metal oxide layers provided between the respective plurality of second interconnections and the third conductive layer and comprising an oxide of a first metal, wherein:
the second interconnection comprises the first metal, and
the second conductive layer and the third conductive layer comprise the oxide of the first metal.

7. The memory device according to claim 6 , wherein the third conductive layer comprises first sections and second sections, the first sections are disposed between the first conductive layer and the respective metal oxide layers and comprise a crystallized oxide of the first metal, and the second sections are disposed between the first sections in the third conductive layer and comprise an amorphous oxide of the first metal.

8. The memory device according to claim 7 , wherein
the first metal is titanium or tungsten.

9. The memory device according to claim 1 , further comprising insulating films disposed between the second interconnections, and wherein
the insulating layer comprising first sections disposed between the respective second interconnections and the first conductive layer, and second sections disposed between the insulating films and the first conductive layer, and
a thickness of the first sections is smaller than a thickness of the second sections.

10. The memory device according to claim 1 , further comprising a plurality of insulating films respectively disposed between the second interconnections, wherein
the first resistance change film further comprises a plurality of insulating layers disposed between the insulating films and the first conductive layer, and isolated from one another.

Assignees

• Toshiba Memory Corp

Inventors

• Hirayama Kana
• Yamamoto Kazuhiko
• Arayashiki Yusuke
• Murakami Yosuke
• Kobayashi Yusuke

Classifications

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/52

  Structure characterized by the electrode material, shape, etc. · CPC title

• G11C2213/32

  Material having simple binary metal oxide structure · CPC title

• G11C2213/71

  Three dimensional array · CPC title