Methods and apparatus for three-dimensional nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9768180-B1
Application number	US-201615338372-A
Country	US
Kind code	B1
Filing date	Oct 29, 2016
Priority date	Oct 29, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

First claim

The invention claimed is:

1. A method comprising:
forming a dielectric material above a substrate;
forming a hole in the dielectric material, the hole disposed in a first direction;
forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer comprising a first conductive material having a first work function;
forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material comprising a semiconductor material layer and a conductive oxide material layer;
forming a local bit line in the hole, the local bit line comprising a second conductive material having a second work function, wherein the first work function is greater than the second work function; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

2. The method of claim 1 , further comprising:
forming a plurality of word line layers above the substrate via the hole, each of the plurality of word line layers disposed in the second direction; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the local bit line and a corresponding one of the word line layers.

3. The method of claim 1 , further comprising:
forming a plurality of holes in the dielectric material, the plurality of holes disposed in the second direction;
forming the word line layer via the plurality of holes;
forming a nonvolatile memory material on a sidewall of each of the holes;
forming a plurality of local bit lines, each local bit line disposed in a corresponding one of the holes; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the word line layer and a corresponding one of the local bit lines.

4. The method of claim 1 , further comprising forming a vertically-oriented transistor above the substrate, and wherein forming the hole comprises forming the hole above the vertically-oriented transistor.

5. The method of claim 1 , further comprising:
forming a global bit line above the substrate, the global bit line disposed in a third direction perpendicular to the first direction and the second direction; and
forming a transistor between the vertical bit line and the global bit line.

6. The method of claim 5 , wherein the transistor comprises a vertical transistor.

7. The method of claim 1 , further comprising:
forming a sacrificial material layer above the substrate;
removing the sacrificial material layer to form a cavity; and
forming the word line layer in the cavity.

8. The method of claim 7 , wherein removing the sacrificial material layer comprises etching the sacrificial material layer via the hole.

9. The method of claim 1 , wherein:
the semiconductor material layer comprises one or more of the group of amorphous silicon, amorphous tantalum nitride, and amorphous tantalum silicon nitride; and
the conductive oxide material layer comprises one or more of the group of crystalline titanium oxide, crystalline zinc oxide, crystalline tungsten oxide, and crystalline praseodymium calcium manganese oxide.

10. The method of claim 1 , wherein:
the first conductive material comprises one or more of the group of tungsten, tungsten nitride, cobalt, and ruthenium; and
the second conductive material comprises one or more of the group of titanium nitride, tantalum nitride, titanium carbide, and tantalum carbide.

11. A method comprising:
forming a sacrificial material layer above a substrate;
etching the sacrificial material layer to form a row of sacrificial material disposed in a first direction;
forming a dielectric material adjacent the row of sacrificial material;
forming a hole in the dielectric material, the hole adjacent the row of sacrificial material and disposed in a second direction perpendicular to the first direction;
replacing the row of sacrificial material with a first conductive material to form a word line layer, the first conductive material comprising a first work function;
forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer;
forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

12. The method of claim 11 , wherein the sacrificial material comprises one or more of the group of a nitride, a silicate glass and a semiconductor material.

13. The method of claim 11 , further comprising:
forming a plurality of sacrificial material layers above the substrate;
etching the plurality of sacrificial material layers to form a row of sacrificial material layers disposed in the first direction;
replacing each of the sacrificial material layers with the first conductive material to form a plurality of word line layers; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the local bit line and a corresponding one of the word line layers.

14. The method of claim 11 , further comprising:
forming a plurality of holes in the dielectric material, the plurality of holes disposed in the first direction, each of the holes adjacent the row of sacrificial material;
forming a nonvolatile memory material on a sidewall of each of the holes;
forming a plurality of local bit lines, each local bit line disposed in a corresponding one of the holes; and
forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the word line layer and a corresponding one of the local bit lines.

15. The method of claim 11 , wherein replacing the sacrificial material layer comprises:
removing the sacrificial material layer to form a cavity; and
forming the conductive material in the cavity.

16. The method of claim 15 , wherein removing the sacrificial material layer comprises etching the sacrificial material layer via the hole.

17. The method of claim 11 , wherein:
the semiconductor material layer comprises one or more of the group of amorphous silicon, amorphous tantalum nitride, and amorphous tantalum silicon nitride; and
the conductive oxide material layer comprises one or more of the group of crystalline titanium oxide, crystalline zinc oxide, crystalline tungsten oxide, and crystalline praseodymium calcium manganese oxide.

18. The method of claim 11 , wherein:
the first conductive material comprises one or more of the group of tungsten, tungsten nitride, cobalt, and ruthenium; and
the second conductive material comprises one or more of the group of titanium nitride, tantalum nitride, titanium carbide, and tantalum carbide.

19. A method of forming a monolithic three-dimensional memory array, the method comprising:
forming a stack of sacrificial material layers above a substrate;
etching the stack of sacrificial material layers to form rows of sacrificial material layers;
forming a dielectric material between the rows of sacrificial material layers;
forming a plurality of holes in the dielectric material, the holes disposed between the

Assignees

• Sandisk Technologies Llc

Inventors

• Zhou Guangle
• Li Yubao
• Chen Yangyin
• Kumar Tanmay

Classifications

• H01L21/30604

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic

• H01L21/823462

  Electricity · mapped topic

• H01L21/823475

  Electricity · mapped topic

• H01L27/115 Primary

  Electricity · mapped topic