Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9252358-B2
Application number	US-201313767029-A
Country	US
Kind code	B2
Filing date	Feb 14, 2013
Priority date	Aug 31, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising a memory cell array comprising: a plurality of first lines and a plurality of second lines intersecting each other; and a plurality of memory cells each disposed at each of intersections of the plurality of first lines and the plurality of second lines and each including a variable resistance element, the method comprising:
stacking a plurality of first conductive layers and a plurality of interlayer insulating layers alternately on a substrate, the first conductive layers functioning as the first lines;
forming a trench that penetrates the plurality of first conductive layers and the plurality of interlayer insulating layers;
forming a side wall layer on a side surface of the plurality of first conductive layers facing the trench and on a side surface of the plurality of interlayer insulating layers facing the trench;
forming a column-shaped conductive layer to fill the trench via the side wall layer, the column-shaped conductive layer functioning as one of the second lines; and
after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, making a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, thereby causing the side wall layer adjacent to the first conductive layers to function as the variable resistance element.

2. The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the first conductive layers are formed by amorphous silicon, and
after formation of the side wall layer, heat treatment is executed to crystallize the amorphous silicon in the first conductive layers into polysilicon.

3. The method of manufacturing a semiconductor memory device according to claim 1 , wherein the side wall layer is formed using ALD.

4. The method of manufacturing a semiconductor memory device according to claim 1 , wherein the interlayer insulating layers are formed using CVD.

5. The method of manufacturing a semiconductor memory device according to claim 1 , wherein the side wall layer is configured by an oxide of any of Hf, Al, Ti, Ni, W, and Ta.

6. The method of manufacturing a semiconductor memory device according to claim 1 , wherein the migration of oxygen atoms occurs after a certain time elapsed after the formation of the side wall layer.

7. The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the side wall layer is formed by a metal oxide in a stoichiometric state, and
after formation of the side wall layer, oxygen atoms in the side wall layer adjacent to the first conductive layers are caused to migrate to the first conductive layers.

8. The method of manufacturing a semiconductor memory device according to claim 7 , wherein
the first conductive layers are formed by amorphous silicon, and
after formation of the side wall layer, heat treatment is executed to crystallize the amorphous silicon in the first conductive layers into polysilicon.

9. The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the side wall layer is formed by a metal oxide in a more oxygen-depleted state than a stoichiometric state, and
after formation of the side wall layer, oxygen atoms in the interlayer insulating layers are caused to migrate to the side wall layer adjacent to the interlayer insulating layers.

10. The method of manufacturing a semiconductor memory device according to claim 9 , wherein the interlayer insulating layers are formed by an oxide in a more oxygen-rich state than a stoichiometric state.

11. The method of manufacturing a semiconductor memory device according to claim 9 , wherein
the first conductive layers are formed by amorphous silicon, and
after formation of the side wall layer, heat treatment is executed to crystallize the amorphous silicon in the first conductive layers into polysilicon.

12. A semiconductor memory device, comprising a memory cell array including a plurality of first lines and a plurality of second lines intersecting each other, and a plurality of memory cells each disposed at each of intersections of the plurality of first lines and the plurality of second lines and each including a variable resistance element,
the memory cell array comprising:
a plurality of first conductive layers aligned with a certain pitch in a perpendicular direction to a substrate and functioning as the first lines;
an interlayer insulating layer provided between the first conductive layers;
a variable resistance layer provided on a side surface of the first conductive layers and functioning as the variable resistance element;
an oxide layer provided on a side surface of the interlayer insulating layer and having a lower conductivity than the variable resistance layer; and
a column-shaped conductive layer provided on a side surface of the first conductive layers via the variable resistance layer and provided on a side surface of the interlayer insulating layer via the oxide layer, the column-shaped conductive layer extending in the perpendicular direction and functioning as one of the second lines, wherein
the oxide layer is configured by a metal oxide in a stoichiometric state, and
the variable resistance layer is configured by a metal oxide in a more oxygen-depleted state than a stoichiometric state.

13. The semiconductor memory device according to claim 12 , further comprising a barrier metal layer provided between a side surface of the variable resistance layer and the column-shaped conductive layer, and between a side surface of the oxide layer and the column-shaped conductive layer,
wherein the barrier metal layer is configured by titanium nitride (TiN).

14. The semiconductor memory device according to claim 12 , further comprising: an N type or P type polycrystalline silicon layer provided between a side surface of the variable resistance layer and the column-shaped conductive layer, and between a side surface of the oxide layer and the column-shaped conductive layer.

15. The semiconductor memory device according to claim 12 , further comprising:
a select transistor having one end connected to one end of the second lines;
a select gate line connected to a gate of the select transistor; and
a third line connected to the other end of the select transistor.

16. The semiconductor memory device according to claim 15 , wherein the memory cell array further comprises:
a second conductive layer extending in a parallel direction to the substrate and functioning as the third line;
a column-shaped semiconductor layer in contact with an upper surface of the second conductive layer and a lower surface of the column-shaped conductive layer, the column-shaped semiconductor layer extending in the perpendicular direction to the substrate and functioning as a body of the select transistor;
a gate insulating layer provided on a side surface of the column-shaped semiconductor layer; and
a third conductive layer provided on a side surface of the column-shaped semiconductor layer via the gate insulating layer, the third conductive layer extending in the parallel direction to the substrate and functioning as the gate of the select transistor and the select gate line.

17. The semiconductor memory device according to claim 16 , wherein

Assignees

• Toshiba Kk

Inventors

• Kanno Hiroshi
• Tsukamoto Takayuki
• Fukumizu Hiroyuki
• Minemura Yoichi
• Okawa Takamasa

Classifications

• H01L45/146

  Electricity · mapped topic

• H01L27/2454

  Electricity · mapped topic

• H01L45/1206 Primary

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic