Vertical cross point arrays for ultra high density memory applications

Patent metadata

Field	Value
Publication number	US-9312307-B2
Application number	US-201414568802-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Aug 15, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F 2 may be realized.

First claim

What is claimed is:

1. A memory structure, comprising:
a front-end of the line (FEOL) portion comprising logic circuitry to perform data operations on memory cells of a vertical cross-point array (VCPA);
a VCPA formed back-end of the line (BEOL) disposed over said FEOL portion, said VCPA comprising horizontal lines, vertical lines, and two-terminal memory cells integrally formed between a center conductor of each vertical line and a respective crossing horizontal line, wherein the horizontal lines comprise conductive lines bounded on both sides by an inner diffusion barrier layer and an outer edge electrode;
a plurality of bit lines;
a plurality of select devices disposed above, and not within said FEOL portion, said plurality of select devices operable to selectively electrically couple the center conductors of the vertical lines of said VCPA to bit lines of said plurality of bit lines; and
at least one of a via or an interconnect to electrically connect bit lines of said plurality of bit lines to the logic circuitry in said FEOL portion.

2. The memory structure of claim 1 , wherein said plurality of bit lines and said plurality of select devices are both disposed in BEOL layers above said VCPA.

3. The memory structure of claim 1 , wherein said plurality of bit lines is disposed in one or more layers above said FEOL portion but below said VCPA.

4. The memory structure of claim 1 , wherein at least one of said plurality of select devices or said plurality of bit lines is disposed in one or more layers below said VCPA but above said FEOL portion.

5. The memory structure of claim 1 , wherein said plurality of bit lines and said plurality of select devices are disposed both in layers above said VCPA and in layers below said VCPA but above said FEOL portion.

6. The memory structure of claim 1 , wherein the horizontal lines of said VCPA are disposed in a plurality of horizontal line layers, each horizontal line layer comprising a plurality of horizontal lines, and said vertical lines are disposed in a plurality of rows such that the plurality of rows of vertical lines are interleaved with the horizontal lines of said plurality of horizontal line layers and a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer.

7. The memory structure of claim 6 , wherein said VCPA has a unit memory cell footprint of 2F 2 , where F is the minimum feature size of the VCPA.

8. The memory structure of claim 1 , wherein the horizontal lines of said VCPA are disposed in a plurality of horizontal line layers, each horizontal line layer comprising a plurality of horizontal lines, and said vertical lines are disposed in a plurality of rows such that the plurality of rows of vertical lines are interleaved with the horizontal lines of said plurality of horizontal line layers and a row of vertical lines is positioned between every other consecutive pair of horizontal lines in each horizontal line layer.

9. The memory structure of claim 8 , wherein said VCPA has a unit memory cell footprint of 4F 2 , where F is the minimum feature size of the VCPA.

10. The memory structure of claim 1 , wherein said select devices comprise at least one of select transistors or diodes.

11. The memory structure of 10, wherein said select transistors or diodes comprise at least one of vertical field-effect transistors (FETs) or metal-insulator-metal (MIM) devices.

12. The memory structure of claim 1 , wherein the center conductor of each vertical line of said VCPA is surrounded or coated in part by a memory film, such that the memory film of a given vertical line is disposed between the center conductor of the given vertical line and horizontal lines that cross the given vertical line.

13. The memory structure of claim 12 , wherein said memory film comprises a resistive change memory film.

14. The memory structure of claim 13 , wherein said resistive change memory film comprises at least one of a metal oxide film, a conductive metal oxide film and an insulating metal oxide film, a chalcogenide film, a ferroelectric film, a ferromagnetic film, a conductive-bridge memory cell, or a carbon nanotube memory cell.

15. The memory structure of claim 1 , wherein each two-terminal memory cell comprises a non-linear I-V characteristic for all values of data stored in the memory cell.

16. The memory structure of claim 1 , wherein a value of a current through each two-terminal memory cell is a non-linear function of a voltage applied across the two-terminal memory cell.

17. The memory structure of claim 1 , wherein the plurality of select devices is disposed in one or more BEOL layers above the VCPA and in one or more BEOL layers below the VCPA.

18. The memory structure of claim 1 , wherein the plurality of select devices is disposed in one or more BEOL layers above the VCPA and in one or more FEOL layers below the VCPA.

19. The memory structure of claim 1 , wherein the plurality of select devices is disposed in one or more BEOL layers above the VCPA and in one or more layers below the VCPA but above the FEOL portion.

20. The memory structure of claim 1 , wherein the plurality of select devices is disposed in one or more layers below the VCPA and the plurality of select devices positioned within said FEOL portion.

Assignees

• Unity Semiconductor Corp

Inventors

• Bateman Bruce Lynn

Classifications

• H01L45/1226

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/2454

  Electricity · mapped topic