Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby

Patent metadata

Field	Value
Publication number	US-9190532-B2
Application number	US-201214240440-A
Country	US
Kind code	B2
Filing date	Aug 8, 2012
Priority date	Aug 24, 2011
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.

First claim

What is claimed is:

1. A non-volatile memory cell comprising:
a single crystalline substrate of a first conductivity type having a top surface;
a first region of a second conductivity type in said substrate along the top surface;
a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region;
a channel region between the first region and the second region;
a word line gate positioned over a first portion of the channel region, immediately adjacent to the first region, said word line gate spaced apart from the channel region by a first insulating layer;
a floating gate positioned over another portion of the channel region, said floating gate having a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface; said floating gate having a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall, wherein said second side wall and said upper surface forming a sharp edge, with said second side wall greater in length than said first side wall and said upper surface having a curved shape that slopes upward from said first side wall to said second side wall;
a coupling gate positioned over the upper surface of the floating gate and insulated therefrom by a third insulating layer, wherein the coupling gate includes a first side wall adjacent to but separated from the word line gate and a second side wall opposite the first side wall of the coupling gate, and a lower surface that includes at least a portion that is disposed over the upward sloping upper surface of the floating gate and that slopes upward from the first side wall of the coupling gate to the second side wall of the coupling gate; and
an erase gate positioned adjacent to the second side wall of the floating gate; said erase gate positioned over the second region and insulated therefrom; said erase gate overhangs a portion of said floating gate.

Assignees

• Wang Chunming
• Qiao Baowei
• Zhang Zufa
• Zhang Yi
• Wang Shiuh Luen
• Lu Wen-Juei
• Silicon Storage Tech Inc

Inventors

• Wang Chunming
• Qiao Baowei
• Zhang Zufa
• Zhang Yi
• Wang Shiuh Luen
• Lu Wen-Juei

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68 Primary

  Floating-gate IGFETs · CPC title