Method of making split-gate memory cell with substrate stressor region

Patent metadata

Field	Value
Publication number	US-9306039-B2
Application number	US-201514665079-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Sep 28, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
providing a substrate of semiconductor material of a first conductivity type;
forming first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, wherein the channel region has first and second portions;
forming a stressor region of embedded silicon carbide in the substrate directly under the second portion of the channel region, wherein no stressor region of embedded silicon carbide is formed directly under the first portion of the channel region;
forming a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and the first portion of the channel region; and
forming a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from the second portion of the channel region and over the stressor region.

2. The method of claim 1 , wherein the second gate has a first portion laterally adjacent to and insulated from the floating gate, and a second portion that extends up and over, and insulated from, the floating gate.

3. The method of claim 1 , further comprising:
forming a conductive program/erase gate laterally to one side of, and insulated from, the floating gate, wherein the program/erase gate is disposed at least partially over and insulated from the first region; and
the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.

4. The method of claim 1 , further comprising:
forming a conductive control gate over and insulated from the floating gate;
forming a conductive erase gate laterally to one side of, and insulated from, the floating gate, wherein the erase gate is disposed at least partially over and insulated from the first region; and
the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.

5. The method of claim 1 , wherein the stressor region is disposed directly under a surface of the substrate such that a surface portion of the substrate over the stressor region is a strained silicon layer and forms the channel region second portion.

6. The method of claim 1 , wherein the forming of the stressor region of embedded silicon carbide in the substrate comprises:
selectively etching semiconductor material from a surface of the substrate to form a recess region in the substrate;
growing silicon carbide in the recess region; and
depositing semiconductor material over the silicon carbide.

Assignees

• Silicon Storage Tech Inc

Inventors

• Tadayoni Mandana
• Do Nhan

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D30/751

  having composition variations in the channel regions · CPC title