Nonvolatile memory devices having single-layered gates

Patent metadata

Field	Value
Publication number	US-2016126247-A1
Application number	US-201514678650-A
Country	US
Kind code	A1
Filing date	Apr 3, 2015
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

First claim

What is claimed is:

1 . A nonvolatile memory device comprising:
an active region extending in a first direction; a first single-layered gate intersecting the active region and extending in a second direction; a second single-layered gate intersecting the active region to be spaced apart from the first single-layered gate in the first direction and extending in the second direction; and a selection gate including a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates, wherein the first selection gate main line is at a side of the first single-layered gate, opposite to the second single-layered gate; and wherein the second selection gate main line is at a side of the second single-layered gate, opposite to the first single-layered gate.

2 . The nonvolatile memory device of claim 1 , wherein the second direction is substantially perpendicular to the first direction.

3 . The nonvolatile memory device of claim 1 , further comprising:
a first impurity junction region disposed in the active region between the first and second single-layered gates; a second impurity junction region disposed in a first end of the active region; a third impurity junction region disposed in a second end of the active region; a fourth impurity junction region disposed in the active region between the first single-layered gate and the first selection gate main line; and a fifth impurity junction region disposed in the active region between the second single-layered gate and the second selection gate main line.

4 . The nonvolatile memory device of claim 3 ,
wherein the first and second single-layered gates are electrically isolated; wherein the selection gate is electrically connected to a word line; wherein the first impurity junction region is electrically connected to a source line; and wherein the second and third impurity junction regions are electrically connected to a bit line.

5 . The nonvolatile memory device of claim 3 , wherein the first to fifth impurity junction regions are doped with N-type impurities.

6 . The nonvolatile memory device of claim 1 , further comprising:
a first gate insulation layer between the first single-layered gate and the active region; a second gate insulation layer between the second single-layered gate and the active region; and a third gate insulation layer between the selection gate and the active region.

7 . The nonvolatile memory device of claim 1 , further comprising:
a first dielectric layer between the first single-layered gate and the first selection gate main line; a second dielectric layer between the second single-layered gate and the second selection gate main line; a third dielectric layer between the first single-layered gate and the selection gate extension; and a fourth dielectric layer between the second single-layered gate and the selection gate extension.

8 . The nonvolatile memory device of claim 7 , wherein a thickness of the third dielectric layer in the first direction is substantially equal to a thickness of the fourth dielectric layer in the first direction.

9 . The nonvolatile memory device of claim 8 , wherein a thickness of each of the third and fourth dielectric layers in the first direction is less than a thickness of each of the first and second dielectric layers in the first direction.

10 . The nonvolatile memory device of claim 1 , wherein the selection gate extension does not overlap with the active region and an end of the selection gate extension is adjacent to the active region.

11 . A nonvolatile memory device comprising:
an active region extending in a first direction; a first single-layered gate intersecting the active region and extending in a second direction; a second single-layered gate intersecting the active region to be spaced apart from the first single-layered gate in the first direction and extending in the second direction; and a selection gate including a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a first selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, a second selection gate interconnection line that connects a second end of the first selection gate main line to a second end of the second selection gate main line, a first selection gate extension that extends from a portion of the first selection gate interconnection line to be disposed between first ends of the first and second single-layered gates, and a second selection gate extension that extends from a portion of the second selection gate interconnection line to be disposed between second ends of the first and second single-layered gates, wherein the first selection gate main line is at a side of the first single-layered gate, opposite to the second single-layered gate; and wherein the second selection gate main line is at a side of the second single-layered gate, opposite to the first single-layered gate.

12 . The nonvolatile memory device of claim 11 , further comprising:
a first impurity junction region in the active region, between the first and second single-layered gates; a second impurity junction region in a first end of the active region; a third impurity junction region in a second end of the active region; a fourth impurity junction region in the active region, between the first single-layered gate and the first selection gate main line; and a fifth impurity junction region in the active region between the second single-layered gate and the second selection gate main line.

13 . The nonvolatile memory device of claim 12 ,
wherein the first and second single-layered gates are electrically isolated; wherein the selection gate is electrically connected to a word line; wherein the first impurity junction region is electrically connected to a source line; and wherein the second and third impurity junction regions are electrically connected to a bit line.

14 . The nonvolatile memory device of claim 11 , further comprising:
a first dielectric layer between the first single-layered gate and the first selection gate main line; a second dielectric layer between the second single-layered gate and the second selection gate main line; a third dielectric layer between the first single-layered gate and the first selection gate extension; a fourth dielectric layer between the second single-layered gate and the first selection gate extension; a fifth dielectric layer between the first single-layered gate and the second selection gate extension; and a sixth dielectric layer between the second single-layered gate and the second selection gate extension.

15 . The nonvolatile memory device of claim 11 ,
wherein the first selection gate extension does not overlap with the active region and an end of the first selection gate extension is adjacent to a first sidewall of the active region, opposite to the second selection gate extension; and wherein the second selection gate extension does not overlap with the active region and an end of the second selectio

Assignees

• Sk Hynix Inc

Inventors

• Kim Jung Hoon
• Park Sung Kun
• Kim Nam Yoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D62/125

  Shapes of junctions between the regions · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title