Chip and method for detecting a change of a stored data vector

Patent metadata

Field	Value
Publication number	US-10216929-B2
Application number	US-201615084533-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.

First claim

What is claimed is:

1. A chip, comprising:
a plurality of processing circuits, each processing circuit being configured to process a data vector by outputting a multiplication of the data vector by one of a plurality of processing matrices, wherein a sum of the respective processing matrices corresponds to a non-identity-matrix part of a generator matrix of a predetermined linear code in reduced form;
a summing circuit configured to sum the output of the data vector processing generated by the processing circuits;
a storage circuit configured to store the data vector with the summed output of the data vector processing as a data word in a memory;
a read-out circuit configured to read the stored data word out of the memory, and
a decoding circuit configured to check whether the read-out data word is a valid code word of the linear code and to output an error signal if the read-out data word is not a valid code word of the linear code and
a monitoring circuit, configured to receive the error signal, and to trigger an execution or a deactivation of a program in response to the error signal.

2. The chip of claim 1 , further comprising:
a plurality of arithmetic logic units (ALUs), each ALU being configured to generate the data vector from an input vector.

3. The chip of claim 2 ,
each processing circuit being connected to the output of a respective ALU and the ALU being configured to supply the data vector to the processing circuit.

4. The chip of claim 3 ,
the memory being connected to the output of one of the ALUs which is configured to supply the data vector to the memory.

5. The chip of claim 1 ,
the data vector representing a command for a processing element of the chip.

6. The chip of claim 5 ,
the processing element being an arithmetic logic unit (ALU) of the chip.

7. The chip of claim 1 ,
each processing matrix having a one per row and otherwise zeros and one or more ones per row and otherwise zeros.

8. The chip of claim 1 ,
the processing matrices being permutation matrices and each processing circuit being a permutation circuit which is configured to permute the data vector in accordance with a permutation matrix.

9. The chip of claim 1 ,
the processing matrices being at least partially different.

10. The chip of claim 1 ,
the non-identity-matrix part being a vector of matrices which can be represented in each case as a sum of processing matrices.

11. The chip of claim 10 ,
each matrix of the matrices being based on a circular matrix.

12. The chip of claim 10 ,
the matrices being matrices determined on the basis of at least one predetermined characteristic of the linear code.

13. The chip of claim 12 ,
the at least one predetermined characteristic being the Hamming distance of the linear code.

14. The chip of claim 1 ,
wherein the decoding circuit is further configured to determine, for a part of the read-out data word corresponding to the data vector, a redundant part of the summed results of the data vector processing and to check whether the redundant part corresponds to the sum generated by the summing circuit.

15. The chip of claim 1 , wherein each of the plurality of processing circuits multiplies the data vector by exactly one processing matrix, and wherein each processing matrix is unique.

16. The chip of claim 1 , wherein each of the plurality of processing circuits is configured to multiply the data vector by a plurality of processing matrices, wherein the sum of the processing matrices corresponds to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form.

17. A chip card comprising a chip, the chip comprising:
a plurality of processing circuits, each processing circuit being configured to process a data vector by outputting a multiplication of the data vector by one of a plurality of processing matrices, wherein a sum of the respective processing matrices corresponds to a non-identity-matrix part of a generator matrix of a predetermined linear code in reduced form;
a summing circuit configured to sum the output of the data vector processing generated by the processing circuits;
a storage circuit configured to store the data vector with the summed output of the data vector processing as a data word in a memory;
a read-out circuit configured to read the stored data word out of the memory, and
a decoding circuit configured to check whether the read-out data word is a valid code word of the linear code and to output an error signal if the read-out data word is not a valid code word of the linear code,
wherein each processing matrix generates by multiplication a new vector from the data vector by selecting for each component of the new vector one or more components of the data vector, each component being selected exactly once.

18. The chip card of claim 17 , wherein the processing matrices are permutation matrices.

19. A method for detecting a change of a stored data vector comprising:
processing a data vector by outputting a multiplication of the data vector by one of a plurality of processing matrices, a sum of the processing matrices corresponding to a non-identity-matrix part of a generator matrix of a predetermined linear code in reduced form;
summing the generated output of the processing operations of the data vector;
storing the data vector with the summed output of the processing operations as a data word in a memory;
reading the stored data word out of the memory, and
checking whether the read-out data word is a valid code word of the linear code and
outputting an error signal if the read-out data word is not a valid code word of the linear code.

Assignees

• Infineon Technologies Ag

Inventors

• Driessen Benedikt
• Sonnekalb Steffen

Classifications

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F21/55 Primary

  Detecting local intrusion or implementing counter-measures · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title