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US-2024402922-A1 · Dec 5, 2024 · US
Memory system having an encoding processing circuit for redundant encoding process
US9105358B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105358-B2 |
| Application number | US-201113157396-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 10, 2011 |
| Priority date | Dec 11, 2008 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.
First claim
Opening claim text (preview).
The invention claimed is: 1. A memory system for writing redundant data output by an encoding processing circuit, comprising: a memory, electrically rewritable by using memory cells capable of having two different resistance values corresponding to logical values of 1 or 0 respectively, the redundant data is read from the memory and a predetermined logical value is written to the memory by flowing current in a same direction; the encoding processing circuit performs redundant en…
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Electricity · mapped topic
- G11C29/42Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9105358B2 cover?
- In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read fro…
- Who is the assignee on this patent?
- Tarui Masaya, Kanai Tatsunori, Yamada Yutaka, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G11C29/42. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).