Memory controller changing partial data in memory device and method for changing partial data thereof

Patent metadata

Field	Value
Publication number	US-9311181-B2
Application number	US-201314071771-A
Country	US
Kind code	B2
Filing date	Nov 5, 2013
Priority date	Nov 15, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A partial data changing method of a memory controller includes receiving a request to change partial data from a host; detecting an error of old data, the old data being partial data read from a memory device using an error detection code; if the old data is not erroneous, calculating a data difference between new data provided from the host and the old data, and calculating a new parity using the data difference and an old parity read from the memory device; and storing the new data and the new parity at the memory device.

First claim

What is claimed is:

1. A partial data changing method of a memory controller comprising:
receiving a request to change partial data from a host;
detecting an error of old data, the old data being partial data read from a memory device;
calculating a data difference between new data provided from the host and the old data;
calculating a new parity using the data difference and an old parity read from the memory device, the old parity being a parity corresponding to the old data, the new parity being a parity corresponding to the new data; and
storing the new data and the new parity at the memory device.

2. The partial data changing method of claim 1 , further comprising:
reading whole data from the memory device when the old data is erroneous; and
correcting the error of the old data using an error correction code, and
wherein the error of the old data is detected using an error detection code, and the calculating the data difference is performed if the old data is not erroneous.

3. The partial data changing method of claim 2 , wherein
the calculating the data difference includes, after the error of the old data is corrected, calculating the data difference between the new data provided from the host and the error-corrected old data, and
the calculating the new parity includes calculating the new parity using the data difference and the old parity read from the memory device.

4. The partial data changing method of claim 3 , further comprising:
performing a partial data encoding operation of dividing whole data to be stored at the memory device into a plurality of partial data, generating a parity for an error detection code of each partial data, and generating partial encoded data.

5. The partial data changing method of claim 4 , further comprising:
performing a whole data encoding operation of generating a parity for an error correction code of all the partial encoded data corresponding to the plurality of partial data after the partial data encoding operation.

6. The partial data changing method of claim 2 , further comprising:
performing a whole data encoding operation including generating a parity for an error correction code of whole data to be stored at the memory device.

7. The partial data changing method of claim 6 , further comprising:
after the whole data encoding operation is performed, dividing the whole data into a plurality of partial data, the whole data being data to be stored at the memory device; and
generating a parity for an error detection code of the whole data.

8. The partial data changing method of claim 7 , further comprising:
performing a partial data encoding operation of generating a parity of an error detection code of each of the plurality of partial data and generating partial encoded data.

9. The partial data changing method of claim 8 , wherein at the partial data encoding operation, encoded parity on the whole data generated at the whole data encoding operation is generated.

10. The partial data changing method of claim 1 , further comprising:
if the old data is erroneous, correcting the error of the old data,
wherein the error of old data is detected using an error correction code, and
wherein, if the error of the old data is corrected, the calculating the data difference is performed between the new data provided from the host and the error-corrected old data.

11. The partial data changing method of claim 10 , further comprising:
storing the new data and the new parity at the memory device.

12. The partial data changing method of claim 10 , further comprising:
performing a partial data encoding operation of dividing whole data to be stored at the memory device into a plurality of partial data, generating a parity for an error correction code of each of the plurality of partial data, and generating partial encoded data; and
performing a whole data encoding operation of generating a parity for an error correction code of all the partial encoded data corresponding to the plurality of partial data after the partial data encoding operation.

13. The partial data changing method of claim 10 , further comprising:
performing a whole data encoding operation of generating a parity for an error correction code of whole data to be stored at the memory device; and
after the whole data encoding operation is performed, dividing the whole data into a plurality of partial data and generating a parity for an error correction code of the whole data.

14. The partial data changing method of claim 13 , further comprising:
performing a partial data encoding operation of generating a parity of an error correction code of each of the plurality of partial data and generating partial encoded data.

15. The partial data changing method of claim 14 , wherein at the partial data encoding operation, an encoded parity on the whole data generated at the whole data encoding operation is generated.

16. The partial data changing method of claim 10 , further comprising:
if the partial data read from the memory device is not erroneous, the calculating the data difference includes calculating the data difference between the new data provided from the host and the old data and the calculating the new parity includes calculating the new parity using the data difference and the old parity read from the memory device.

17. The partial data changing method of claim 10 , wherein the memory device is a volatile memory device.

18. The partial data changing method of claim 10 , wherein the memory device is a nonvolatile memory device.

19. A memory controller for generating a new parity when partial data of a memory device is changed, comprising:
a data location identifier configured to identify a location of the changed partial data;
a data difference calculator configured to receive location information of the changed partial data from the data location identifier and to calculate a data difference between new data input from a host and old data input from the memory device; and
a parity calculator configured to calculate the new parity using an old parity stored at the memory device and the data difference, the old parity being a parity corresponding to the old data, the new parity being a parity corresponding to the new data.

20. The memory controller of claim 19 , wherein the data location identifier, the data difference calculator, and the parity calculator are included in a new parity generator.

21. The memory controller of claim 19 , wherein the data difference calculator is configured to process unmodified data of data stored at the memory device to be set to 0 and calculate the data difference between the new data and the old data.

22. The memory controller of claim 19 , wherein the data difference calculator is configured to divide the changed partial data into a plurality of sections and calculate the data difference between the new data and the old data with respect to each of the plurality of sections.

23. The memory controller of claim 19 , wherein the data difference calculator is configured to calculate the data difference between the new data and the old data using an XOR operation.

24. A memory system comprising:
a memory device configured to store data and a parity;
a host configured to provide new data for changing partial data stored at the memory device and location information of the changed partial data; and
a memory controller configured to receive the new data and the locatio

Assignees

• Lee Kijun
• Kong Junjin
• Son Hong Rak
• Lim Sejin
• Samsung Electronics Co Ltd

Inventors

• Lee Kijun
• Kong Junjin
• Son Hong Rak
• Lim Sejin

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F11/1435

  using file system or storage system metadata · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/2942

  wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title