Sequential timing using level-sensitive clocked elements to optimize IC performance

Patent metadata

Field	Value
Publication number	US-9436794-B2
Application number	US-201414582971-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 30, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A method of optimizing timing performance of an IC design expressed as a graph that includes several nodes representing IC components is provided. The method identifies several paths in the graph. Each path starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths to satisfy timing constraints. The method identifies a path that includes a set of edge-triggered clocked elements and does not satisfy the set of timing constraints. The method replaces each edge-triggered clocked element in the identified path with a level-sensitive clocked element and optimizes the timing performance of the IC design by skewing clock signals one or more clocked element in the identified path.

First claim

What is claimed is:

1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising:
identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements;
optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths in the plurality of paths that fails to satisfy a set of timing constraints;
identifying a path in the plurality of paths that (i) comprises a set of edge-triggered clocked elements and (ii) does not satisfy the set of timing constraints;
replacing each edge-triggered clocked element in the identified path with a level-sensitive clocked element;
after said replacing, optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in said identified path; and
implementing the IC design using the optimized IC design.

2. The method of claim 1 , wherein at least one of the edge-triggered clocked elements is a register.

3. The method of claim 1 , wherein at least one of the edge-triggered clocked elements is a flip flop.

4. The method of claim 1 , wherein at least one of the level-sensitive clocked element is a latch.

5. The method of claim 1 , wherein a timed node is one of primary input through which the IC receives external inputs, a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.

6. The method of claim 1 , wherein a timed node is one of primary input through which the IC receives external inputs, a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.

7. The method of claim 1 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.

8. A non-transitory machine readable medium storing a program for optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the program executable by at least one processing unit, the program comprising sets of instructions for:
identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements;
optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths in the plurality of paths that fails to satisfy a set of timing constraints;
identifying a path in the plurality of paths that (i) comprises a set of edge-triggered clocked elements and (ii) does not satisfy the set of timing constraints;
replacing each edge-triggered clocked element in the identified path with a level-sensitive clocked element;
after said replacing, optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in said identified path; and
implementing the IC design using the optimized IC design.

9. The non-transitory machine readable medium of claim 8 , wherein at least one of the edge-triggered clocked elements is a register.

10. The non-transitory machine readable medium of claim 8 , wherein at least one of the edge-triggered clocked elements is a flip flop.

11. The non-transitory machine readable medium of claim 8 , wherein at least one of the level-sensitive clocked element is a latch.

12. The non-transitory machine readable medium of claim 8 , wherein a timed node is one of primary input through which the IC receives external inputs, a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.

13. The non-transitory machine readable medium of claim 8 , wherein a timed node is one of primary input through which the IC receives external inputs, a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.

14. The non-transitory machine readable medium of claim 8 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.

15. A device comprising:
a set of processing units; and
a non-transitory machine readable medium storing a program for execution by at least one of the processing units, the program for optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the program comprising sets of instructions for:
identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements;
optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths in the plurality of paths that fails to satisfy a set of timing constraints;
identifying a path in the plurality of paths that (1) comprises a set of edge-triggered clocked elements and (ii) does not satisfy the set of timing constraints;
replacing each edge-triggered clocked element in the identified path with a level-sensitive clocked element;
after said replacing, optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in said identified path; and

implementing the IC design using the optimized IC design.

16. The non-transitory machine readable medium of claim 15 , wherein at least one of the edge-triggered clocked elements is a register.

17. The non-transitory machine readable medium of claim 15 , wherein at least one of the edge-triggered clocked elements is a flip flop.

18. The non-transitory machine readable medium of claim 15 , wherein at least one of the level-sensitive clocked element is a latch.

19. The non-transitory machine readable medium of claim 15 , wherein a timed node is one of primary input through which the IC receives external inputs, a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.

20. The non-transitory machine readable medium of claim 15 , wherein a timed node is one of primary input through which the IC receives external inputs, a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.

21. The non-transitory machine readable medium of claim 15 , wherein the IC is one of an application-specific

Assignees

• Altera Corp

Inventors

• Teig Steven
• Caldwell Andrew

Classifications

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title