Layout design system, system and method for fabricating mask pattern using the same

Patent metadata

Field	Value
Publication number	US-10216082-B2
Application number	US-201615001854-A
Country	US
Kind code	B2
Filing date	Jan 20, 2016
Priority date	Apr 14, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.

First claim

What is claimed is:

1. A layout design system comprising:
a layout designer including,
a processor, and
a storage unit coupled to the processor,
the storage unit configured to store a layout design and a stitch module,
the layout design including a first pattern group and a second pattern group disposed in accordance with a design,
the first pattern group including a first pattern for patterning at a first time,
the second pattern group including a second pattern for patterning at a second time that is different than the first time,
the processor, in response to executing the stitch module, being configured to detect an iso-pattern of the second pattern,
the processor, in response to executing stitch module, being configured to modify the second pattern group by designating at least one structure of the first pattern, which is spaced apart from the iso-pattern by a desired pitch or more, to the second pattern group such that the at least one structure of the first pattern is repetitively designated in the first pattern group and the second pattern group,

the desired pitch corresponding to a minimum pitch for limiting an occurrence of a bridge; and
a mask pattern former configured to form a first mask pattern corresponding to the first pattern at the first time and to form a second mask pattern corresponding to the second pattern at the second time based on the layout design, the mask pattern former being configured to form the first pattern at the first time and the second pattern at the second time on a tangible layer.

2. The layout design system of claim 1 , wherein
the storage unit is configured to store a cutting module, and
the processor, in response to executing the cutting module, is configured to divide the layout design into a plurality of sub-layout designs.

3. The layout design system of claim 2 , wherein the processor, in response to executing the cutting module, is configured to divide the layout design so the iso-pattern exists alone in one of the sub-layout designs.

4. The layout design system of claim 2 , wherein the processor, in response to executing the cutting module, is configured to base a length of the sub-layout designs on an etch skew.

5. The layout design system of claim 1 , wherein
the storage unit is configured to store a decomposition module,
the processor, in response to executing the decomposition module, is configured to supply the storage unit with a pre layout design including a plurality of patterns,
the processor is configured to convert the plurality of patterns into nodes, and
the processor is configured to generate a link connecting the nodes to classify the plurality of patterns into the first pattern group or the second pattern group and form the layout design.

6. The layout design system of claim 5 , wherein the processor, in response to executing the decomposition module, is configured to classify the nodes sharing the link into different groups of each of the first pattern group and the second pattern group.

7. The layout design system of claim 6 , wherein
the processor, in response to executing the decomposition module, is configured to classify a pattern, which cannot be classified into both the first pattern group and the second pattern group, into a conflict pattern,
the conflict pattern includes a first region and a second region partially overlapping each other,
the processor, in response to executing the stitch module, is configured to classify the first region into the first pattern group,
the processor, in response to executing the stitch module, is configured to classify the second region into the second pattern group, and
the processor, in response to executing the stitch module, is configured to repetitively designate a region in which the first region and the second region overlap each other in the first pattern group and the second pattern group.

8. The layout design system of claim 7 , wherein the processor, in response to executing the stitch module, is configured to determine the first region and the second region in accordance with a design rule.

9. The layout design system of claim 1 , wherein
the first pattern includes a plurality of first pattern structures,
the second pattern includes a plurality of second pattern structures and the iso-pattern,
the processor, in response to executing the stitch module, is configured to modify the second pattern group by designating the at least one of the plurality of first pattern structure using a first repetitive designation operation and a second repetitive designation operation,
the first repetitive designation operation includes designating a first number of the plurality of first patterns structures that are spaced apart from the iso-pattern by the desired pitch or more into the second pattern group to form a first repetitively designated first pattern, and
the second repetitive designation operation includes designating a second number of the plurality of first patterns structures that are spaced apart from the first repetitively designated first pattern by the desired pitch or more into the second pattern group.

10. The layout design system of claim 1 , wherein
the layout design includes a conflict pattern,
the conflict pattern includes a superposition region and a non-superposition region that do not overlap each other,
the processor, in response to executing the stitch module, is configured to repetitively designate the superposition region of the conflict pattern into the first pattern and the second pattern, and divide a designation of the non-superposition region such that a first portion of non-superposition region is designated into the first pattern and a second portion of the non-superposition region is designated into the second pattern.

11. The layout design system of claim 10 , wherein the processor is configured to determine a length of the superposition region in consideration of an etch skew.

12. The layout design system of claim 1 , wherein a design rule includes separation between the first pattern and the second pattern by a regular pitch or more.

13. The layout design system of claim 1 , wherein the first time is faster than the second time.

14. The layout design system of claim 1 , wherein
the layout designer is configured to modify the layout from a first layout to a second layout,
the first layout having at least one structure of the first pattern designated in the first pattern group but not the second pattern group, and
the second layout having the least one structure of the first pattern repetitively designated in the first pattern group and the second pattern group.

15. The layout design system of claim 14 , further comprising: an etch skew corrector configured to correct critical dimensions of the first and second patterns of the second layout.

16. The layout design system of claim 1 , further comprising:
a layout designer including a storage unit, a decomposition module, a stitch module, and the processor,
the storage unit being configured to store a layout design,
the processor, in response to executing the decomposition module, being configured to decompose the layout design into a plurality of pattern groups, using the processor,
the plurality of pattern groups including a third pattern group including a third pattern, the first pattern group including a plurality of first patterns for patterning at a first time, and the second pattern group including a plurality of second patterns for patterning at the second time after the first time,
the plurality of first patterns including the first pattern,
the pl

Assignees

• Kang Dae Kwon
• Jung Ji Young
• Kim Dong Gyun
• Yang Jae Seok
• Park Sung Keun
• Park Young Gook
• Samsung Electronics Co Ltd

Inventors

• Kang Dae-Kwon
• Jung Ji-Young
• Kim Dong-Gyun
• Yang Jae-Seok
• Park Sung-Keun
• Park Young-Gook

Classifications

• G03F7/70433

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/00

  Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof · CPC title

• G21K5/00

  Irradiation devices (discharge tubes for irradiating H01J37/00) · CPC title