Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9846754-B2
Application number	US-201615079640-A
Country	US
Kind code	B2
Filing date	Mar 24, 2016
Priority date	Aug 6, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor device can be manufactured based on patterning groups to include a metal layer patterned according to separate patterning groups. The patterning groups are based on a layout pattern. Preparing the layout pattern includes selecting a first power pattern and a second power pattern, selecting a first pattern and a second pattern therebetween, and selecting a tie-connection pattern to connect the first power pattern to the first pattern. The manufacturing includes forming metal lines according to the patterning groups. Photomasks are manufactured according to the layout pattern, and the metal lines are formed according to the photomasks. A first photomask is manufactured based on the first power pattern and the second power pattern, the first pattern, and the tie-connection pattern, and a second photomask is manufactured based on the second pattern.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
preparing a layout pattern, the preparing including:
selecting a first power pattern and a second power pattern,
selecting a first pattern and a second pattern between the first power pattern and the second power pattern, and
selecting a tie-connection pattern connecting the first power pattern to the first pattern;

manufacturing a first photomask based on the first power pattern, the second power pattern, the first pattern, and the tie-connection pattern;
manufacturing a second photomask based on the second pattern; and
forming one or more metal lines on a substrate according to the first photomask and the second photomask.

2. The method of claim 1 , wherein,
at least one of the metal lines includes a power interconnection portion, a metal interconnection portion, and a tie interconnection portion that are connected to form a single body; and
a position and a shape of each of the power interconnection portion, the metal interconnection portion, and the tie interconnection portion is at least partially defined by the first power pattern, the first pattern, and the tie-connection pattern, respectively.

3. The method of claim 1 , wherein the first pattern is configured to define an input pattern to which an input signal is applied.

4. The method of claim 1 , wherein the tie-connection pattern includes a geodesic connection of the first power pattern to the first pattern.

5. The method of claim 1 , wherein,
the preparing the layout pattern further includes,
preparing back-annotation information indicating tie-connection availability between the first pattern and the second pattern and the first power pattern and the second power pattern.

6. The method of claim 5 , wherein,
the preparing back-annotation information includes,
identifying first preliminary tie-connection patterns configured to connect the first power pattern to the first pattern and the second pattern, respectively;
identifying second preliminary tie-connection patterns configured to connect the second power pattern to the first pattern and the second pattern, respectively; and
excluding one of the first preliminary tie-connection patterns and the second preliminary tie-connection patterns from the back-annotation information based on a determination that the one of the first preliminary tie-connection patterns and the second preliminary tie-connection patterns violates at least one design rule.

7. The method of claim 5 , wherein,
the back-annotation information includes first information indicating that the first pattern is configured to be connected to the first power pattern by at least one tie-connection pattern; and
said at least one tie-connection pattern is selected based on the first information.

8. The method of claim 5 , wherein,
the back-annotation information includes,
first information indicating that the first pattern is configured to be connected to the first power pattern by at least one tie-connection pattern, and
second information indicating that the second pattern is restricted from being connected to the first power pattern by at least one tie-connection pattern;

the first pattern and the second pattern are input patterns and are functionally equivalent to each other; and
the selecting the tie-connection pattern includes,
determining whether the second pattern is a first input pattern configured to be connected to the first power pattern, and
selecting the tie-connection pattern to connect the first power pattern to the first pattern, based on the back-annotation information, such that the first pattern is assigned to a second input pattern, the second input pattern being functionally equivalent to the first input pattern.

9. The method of claim 5 , wherein,
the first power pattern and the second power pattern and the second pattern are included in a first patterning group associated with manufacturing the first photomask;
the first pattern is included in a second patterning group associated with manufacturing the second photomask;
the back-annotation information indicating that the first pattern is restricted from being connected to the first power pattern by at least one tie-connection pattern; and
the selecting the tie-connection pattern includes,
determining whether the first pattern is an input pattern configured to be connected to the first power pattern,
converting the first pattern from the second patterning group to the first patterning group, based on the back-annotation information, and
converting the second pattern from the first patterning group to the second patterning group, based on the back-annotation information.

10. The method of claim 1 , prior to the forming one or more metal lines, further comprising:
patterning the substrate to define an active pattern;
forming a gate pattern that crosses the active pattern; and
forming a source region and a drain region on the active pattern and at opposite sides of the gate pattern,
wherein at least two of the metal lines are electrically connected to the gate pattern, the source region and the drain region, respectively.

11. A method of manufacturing a semiconductor device, the method comprising:
preparing a layout pattern for a first metal layer, the preparing including:
selecting a pair of power patterns,
selecting a plurality of patterns between the pair of power patterns,
selecting a tie-connection pattern to connect at least one power patterns of the pair of the power patterns to at least one pattern of the plurality of patterns, and
assigning the pair of the power patterns, the at least one patterns, and the tie-connection pattern to a first patterning group; and

forming metal lines on a substrate, the metal lines having positions and shapes defined by the layout pattern for the first metal layer.

12. The method of claim 11 , wherein,
the forming the metal lines includes performing a patterning process according to a first photomask and a second photomasks; and
the first photomask is manufactured based on the first patterning group.

13. The method of claim 11 , wherein,
the preparing the layout pattern for the first metal layer further includes,
preparing back-annotation information indicating tie-connection availability between the plurality of patterns and the pair of power patterns.

14. The method of claim 13 , wherein,
the selecting the tie-connection pattern includes,
determining a connection relationship criterion, based on the back-annotation information; and
selecting the tie-connection pattern if a connection relationship between an input pattern of the plurality of patterns and the pair of power patterns at least meets the connection relationship criterion.

15. The method of claim 13 , wherein,
the selecting the tie-connection pattern includes,
determining a connection relationship criterion, based on the back-annotation information; and
if a connection relationship of an input pattern of the plurality of patterns does not meet the connection relationship criterion, performing at least one of,
replacing the input pattern with another pattern of the plurality of patterns, and
assigning the input pattern to the first patterning group.

16. A method of manufacturing a semiconductor device, the method comprising:
forming at least one insulating layer on a substrate;
forming at least a first set and a second sets of metal interconnection holes in the at least one insulating layer according to separate, respective a first patterning group and a second pat

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bae Sungmin
• Kim Tae-Il

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title