Method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9831244-B2
Application number	US-201514838983-A
Country	US
Kind code	B2
Filing date	Aug 28, 2015
Priority date	Oct 9, 2012
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region, a second region and a plurality of isolation regions including a first isolation region and a second isolation region, the first isolation region being disposed between the first region and the second region;
a first gate structure disposed in the first region of the substrate, the first gate structure including a first gate insulation film pattern, a first metal gate film pattern disposed on the first gate insulation film pattern, a second metal gate film pattern disposed in a first trench defined by the first metal gate film pattern and filling the first trench, and a third metal gate film pattern disposed on the second metal gate film pattern;
a first high-k film pattern disposed between the first gate insulation film pattern and the first metal gate film pattern; and
a second gate structure disposed in the second region of the substrate, the second gate structure including a second gate insulation film pattern, a fourth metal gate film pattern disposed on the second gate insulation film pattern, a fifth metal gate film pattern disposed in a second trench defined by the fourth metal gate film pattern and filling the second trench, and a sixth metal gate film pattern disposed on the fifth metal gate film pattern,
wherein the first metal gate film pattern directly contacts the third metal gate film pattern,
wherein a width of the first metal gate film pattern is equal to a width of the third metal gate film pattern, and
wherein an upper surface of the third metal gate film pattern is lower than an upper surface of the first high-k film pattern.

2. The semiconductor device of claim 1 , wherein a width of the second metal gate film pattern is greater than a width of the fifth metal gate film pattern.

3. The semiconductor device of claim 1 , wherein the first metal gate film pattern directly contacts a bottom surface of the third metal gate film pattern.

4. The semiconductor device of claim 1 , further comprising a first blocking layer pattern covering the third metal gate film pattern.

5. The semiconductor device of claim 4 , wherein a depth of the first blocking layer pattern is smaller than a depth of the third metal gate film pattern.

6. The semiconductor device of claim 4 , wherein a width of the first blocking layer pattern is equal to the width of the third metal gate film pattern.

7. The semiconductor device of claim 4 ,
wherein an upper surface of the first blocking layer pattern is higher than the upper surface of the first high-k film pattern, and a bottom surface of the first blocking layer pattern is lower than the upper surface of the first high-k film pattern.

8. The semiconductor device of claim 1 , further comprising:
a first spacer disposed along a first side of the first gate structure and a second spacer disposed along a second side of the first gate structure; and
a third spacer disposed along a first side of the second gate structure and a fourth spacer disposed along a second side of the second gate structure,
wherein the first spacer, the second spacer, the third spacer, and the fourth spacer are each dual spacers that include an elliptical sector-shaped first sub-spacer and a rectangular-shaped second sub-spacer.

9. The semiconductor device of claim 1 , wherein a depth of the second metal gate film pattern is greater than a depth of the fifth metal gate film pattern.

10. The semiconductor device of claim 1 , wherein the second metal gate film pattern is formed of a same material as the third metal gate film pattern, and the fifth metal gate film pattern is formed of a same material as the sixth metal gate film pattern.

11. The semiconductor device of claim 1 , wherein the second metal gate film pattern directly contacts the third metal gate film pattern, and the fifth metal gate film pattern directly contacts the sixth metal gate film pattern.

12. The semiconductor device of claim 1 , wherein the first metal gate film pattern is U-shaped, and the fourth metal gate film pattern is U-shaped, and
wherein a width of each side portion of the U-shaped first metal gate film pattern is less than a width of each side portion of the U-shaped fourth metal gate film pattern.

13. A semiconductor device comprising:
a substrate including an isolation region; and
a gate structure disposed on the substrate, the gate structure including a gate insulation film pattern, a U-shaped high-k film pattern disposed on the gate insulation film pattern, a U-shaped first metal gate film pattern disposed on the U-shaped high-l film pattern, a second metal gate film pattern disposed in a trench defined by the U-shaped first metal gate film pattern and filling the trench, a third metal gate film pattern disposed on the second metal gate film pattern, and a first blocking layer pattern disposed on the third metal gate film pattern,
wherein a width of the first blocking layer pattern is equal to a width of the third metal gate film pattern.

14. The semiconductor device of claim 13 , wherein the second metal gate film pattern directly contacts the third metal gate film pattern.

15. The semiconductor device of claim 13 , Wherein a depth of the first blocking layer pattern is smaller than a depth of the third metal gate film pattern.

16. The semiconductor device of claim 13 , further comprising:
a silicide disposed on the substrate, and disposed between the gate structure and the isolation region; and
a contact disposed partially on the silicide and partially on the gate structure.

17. The semiconductor device of claim 13 , Wherein a depth of the second metal gate film pattern is larger than a depth of the third metal gate film pattern.

18. A semiconductor device comprising:
a substrate including an isolation region; and
a gate structure disposed on the substrate, the gate structure including a gate insulation film pattern, a U-shaped high-k film pattern disposed on the gate insulation film pattern, a U-shaped first metal gate film pattern disposed on the U-shaped high-k film pattern, a second metal gate film pattern disposed in a trench defined by the U-shaped first metal gate film pattern and filling the trench, a third metal gate film pattern disposed on the second metal gate film pattern, and a first blocking layer pattern disposed on the third metal gate film pattern,
wherein a depth of the first blocking layer pattern is smaller than a depth of the third metal gate film pattern.

19. The semiconductor device of claim 18 , the first blocking layer pattern is disposed between side portions of the U-shape high-k film pattern.

20. The semiconductor device of claim 19 , the first blocking layer pattern does not cover each upper surface of the side portions of the U-shape high-k film pattern.

Assignees

• Kim Ju-Youn
• Kim Je-Don
• Samsung Electronics Co Ltd

Inventors

• Kim Ju-Youn
• Kim Je-Don

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title