Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9779997-B2
Application number	US-201615068409-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Dec 31, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a dummy gate structure over a substrate;
forming a first insulating layer over the dummy gate structure, the dummy gate structure including a dummy gate electrode layer and sidewall spaces disposed on opposing side faces of the dummy gate electrode layer;
removing the dummy gate electrode layer so as to form a gate space;
forming a gate dielectric layer in the gate space and on a top of the sidewall spacers and on the first insulating layer;
forming a first conductive layer on the gate dielectric layer in the gate space so as to form a reduced gate space;
filling the reduced gate space with a second conductive layer made of a different material from the first conductive layer;
removing the gate dielectric layer formed on the top of the sidewall spacers and on the first insulating layer;
after the gate dielectric layer is removed, recessing the filled first conductive layer and the second conductive layer so as to form a first gate recess; and
forming a third conductive layer over the first conductive layer and the second conductive layer in the first gate recess, wherein:
after recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer, and
the method further comprises, between the removing the gate dielectric layer and the recessing the filled first conductive layer and the second conductive layer, recessing the first insulating layer, the sidewall spacers, the gate dielectric layer, and the first and second conductive layers.

2. The method of claim 1 , further comprising forming a fourth conductive layer over the second conductive layer before forming the third conductive layer.

3. The method of claim 2 , further comprising:
recessing the third conductive layer so as to form a second gate recess; and
forming a second insulating layer over the recessed third conductive layer in the second gate recess.

4. The method of claim 1 , wherein a material of the second conductive layer is the same as a material of the third conductive layer.

5. The method of claim 1 , wherein a material of the second conductive layer includes at least one of W, Co, Ti, Al, and Cu.

6. The method of claim 1 , wherein a material of the first conductive layer includes at least one of TiN, Al, TaAlC and TiAl.

7. The method of claim 1 , wherein a material of the fourth conductive layer includes at least one of TiN, TaN and Ti.

8. A method of manufacturing a semiconductor device, the method comprising:
forming a first dummy gate structure for a first field effect transistor (FET) having a gate length Lg 1 in a first region and a second dummy gate structure for a second FET having a gate length Lg 2 in a second region, Lg 2 being greater than Lg 1 ;
forming a first insulating layer over the first and second dummy gate structures;
removing the first and second dummy gate structures so as to form a first gate space and a second gate space, respectively, in the first insulating layer;
forming a first first-conductive layer in the first gate space so as to form a first reduced gate space and a second first-conductive layer in the second gate space so as to form a second reduced gate space;
filling the first reduced gate space with a first second-conductive layer made of a different material from the first first-conductive layer and the second reduced gate space with a second second-conductive layer made of a different material from the second first-conductive layer;
covering the second region with a mask layer;
recessing the filled first first-conductive layer and the first second-conductive layer so as to form a first gate recess, while the second region is covered with the mask layer;
forming a third conductive layer over the first first-conductive layer and the first second-conductive layer in the first gate recess, while the second region is covered with the mask layer;
after forming the third conductive layer, removing the mask layer; and
recessing the third conductive layer in the first region and the second first-conductive layer and the second second-conductive layer in the second region.

9. The method of claim 8 , wherein after recessing the filled first first-conductive layer and the first second-conductive layer, the first second-conductive layer protrudes from the first first-conductive layer.

10. The method of claim 8 , wherein after recessing the third conductive layer in the first region and the second first-conductive layer and the second second-conductive layer in the second region, the second second-conductive layer protrudes from the second first-conductive layer.

11. The method of claim 8 , wherein after recessing the third conductive layer in the first region and the second first-conductive layer and the second second-conductive layer in the second region, a height of the recessed third conductive layer from a substrate is different from a height of the recessed second second-conductive layer from the substrate.

12. The method of claim 8 , further comprising forming a fourth conductive layer over the first second-conductive layer before forming the third conductive layer.

13. The method of claim 8 , further comprising, after recessing the third conductive layer in the first region and the second first-conductive layer and the second second-conductive layer in the second region, forming a second insulating layer over the recessed third conductive layer and the recessed second second-conductive layer and second first-conductive layer.

14. The method of claim 8 , wherein a material of the first second-conductive layer is the same as a material of the third conductive layer.

15. The method of claim 8 , wherein a material of the first and second second-conductive layers includes at least one of W, Co, Ti, Al, and Cu.

16. The method of claim 8 , wherein a material of the first and second first-conductive layers includes at least one of TiN, Al, TaAlC and TiAl.

17. The method of claim 8 , wherein a material of the fourth conductive layer includes at least one of TiN, TaN and Ti.

18. A semiconductor device comprising:
a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode, the first FET having a gate length Lg 1 ; and
a second FET including a second gate dielectric layer and a second gate electrode, the second FET having a gate length Lg 2 greater than Lg 1 , wherein:
the first gate electrode includes a first lower conductive layer, a first upper conductive layer and an intermediate conductive layer disposed between the first lower conductive layer and the first upper conductive layer,
the first lower conductive layer includes a first underlying conductive layer in contact with the first gate dielectric layer and a first bulk conductive layer,
the first bulk conductive layer protrudes from the first underlying conductive layer,
the second gate electrode includes a second underlying conductive layer and a second bulk conductive layer,
a bottom of the second underlying conductive layer is in contact with the second gate dielectric layer,
an insulating layer is provided in contact with an upper surface of the second underlying conductive layer and an upper surface of the second gate dielectric layer.

19. The semiconductor device of claim 18 , wherein a height of the first upper conductive layer from a substrate is different from a height of the second bulk conductive layer from the subs

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Po-Hsueh
• Yeh Chih-Yang
• Hsiao Chun-Chan
• Yeh Kuan-Lin
• Huang Yuan-Sheng

Classifications

• H01L21/823431

  Electricity · mapped topic

• H01L21/823456 Primary

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic