Semiconductor devices with conductive contact structures having a larger metal silicide contact area

Patent metadata

Field	Value
Publication number	US-2016190339-A1
Application number	US-201615065998-A
Country	US
Kind code	A1
Filing date	Mar 10, 2016
Priority date	May 21, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material.

First claim

What is claimed:

1 . A semiconductor device, comprising:
a source/drain region; a gate structure; a gate cap layer positioned above said gate structure; a sidewall spacer positioned adjacent to opposite sides of said gate structure; a first epi semiconductor material positioned in said source/drain region, said first epi semiconductor material having a first lateral width at an upper surface thereof; a second epi semiconductor material positioned on said first epi semiconductor material, said second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of said sidewall spacer and having a second lateral width at an upper surface thereof that is greater than said first lateral width; and a metal silicide region positioned on said upper surface of said second epi semiconductor material.

2 . The semiconductor device of claim 1 , wherein said first and second epi semiconductor materials comprise a same semiconductor material.

3 . The semiconductor device of claim 1 , wherein said second epi semiconductor material extends laterally over and covers a portion of said gate cap layer.

4 . The semiconductor device of claim 1 , further comprising a layer of insulating material positioned above said gate cap layer and said sidewall spacer, wherein said second epi semiconductor material extends laterally over and covers a portion of said layer of insulating material.

5 . The semiconductor device of claim 1 , wherein said gate structure comprises a gate insulation layer and a gate electrode positioned above said gate insulation layer.

6 . The semiconductor device of claim 5 , wherein said gate insulation layer comprises a high-k dielectric material and said gate electrode comprises at least one layer of a work function adjusting metal material.

7 . The semiconductor device of claim 5 , wherein said gate insulation layer comprises silicon dioxide and said gate electrode comprises a layer of polysilicon.

8 . The semiconductor device of claim 1 , further comprising a conductive contact structure that is conductively coupled to said metal silicide region.

9 . The semiconductor device of claim 1 , wherein said first epi semiconductor material directly contacts a channel region of said semiconductor device.

10 . The semiconductor device of claim 9 , wherein said semiconductor device is a nanowire device and said channel region comprises a plurality of vertically spaced-apart nanowires.

11 . The semiconductor device of claim 9 , wherein said semiconductor device is a gate-all-around FinFET device and said channel region comprises a vertically elongated fin structure.

12 . A nanowire device, comprising:
a stacked nanowire structure comprising a plurality of vertically spaced-apart nanowires; a source/drain region positioned adjacent to said stacked nanowire structure; a gate structure positioned around and above said stacked nanowire structure; a gate cap layer positioned above said gate structure; a sidewall spacer positioned adjacent to opposite sides of said gate structure; a layer of insulating material positioned above said gate cap layer and above an uppermost end of said sidewall spacer; a first epi semiconductor material positioned in said source/drain region, said first epi semiconductor material directly contacting an end surface of each of said plurality of vertically spaced-apart nanowires and having a first lateral width at an upper surface thereof; and a second epi semiconductor material positioned on said first epi semiconductor material and having a second lateral width at an upper surface thereof that is greater than said first lateral width, said second epi semiconductor material extending laterally over and covering at least a portion of said layer of insulating material and at least a portion of said uppermost end of said sidewall spacer.

13 . The nanowire device of claim 12 , further comprising a metal silicide region positioned on said upper surface of said second epi semiconductor material.

14 . The nanowire device of claim 13 , further comprising a conductive contact structure that is conductively coupled to said metal silicide region.

15 . The semiconductor device of claim 12 , wherein said first and second epi semiconductor materials comprise a same semiconductor material.

16 . The semiconductor device of claim 12 , wherein said gate structure comprises a gate insulation layer comprising silicon dioxide and a gate electrode comprising a layer of polysilicon material positioned above said gate insulation layer.

17 . The nanowire device of claim 12 , wherein each of said plurality of vertically spaced-apart nanowires has an outer perimeter when viewed in a cross-section taken through each of said respective nanowires in a direction corresponding to a gate width direction of said nanowire device, said gate structure comprising:
a gate insulation layer positioned around said outer perimeter of each of said plurality of vertically spaced-apart nanowires, said gate insulation layer comprising a high-k dielectric material; at least one work function adjusting metal layer positioned around said gate insulation layer and said outer perimeter of each of said plurality of vertically spaced-apart nanowires, wherein said at least one work function adjusting metal layer has an upper surface that is positioned above an upper surface of said plurality of vertically spaced-apart nanowires; and at least one conductive material positioned above said upper surface of said work function adjusting metal layer, wherein said gate cap layer is positioned above said at least one conductive material.

18 . A nanowire device, comprising:
laterally spaced-apart first and second stacked nanowire structures, each of said first and second stacked nanowire structures comprising a plurality of vertically spaced-apart nanowires, wherein each nanowire of said plurality of vertically spaced-apart nanowires has an outer perimeter when viewed in a cross-section taken through each of said respective nanowires in a direction corresponding to a gate width direction of said nanowire device; a layer of insulating material positioned between said laterally spaced-apart first and second stacked nanowire structures; a gate insulation layer positioned around said outer perimeter of each nanowire of said plurality of vertically spaced-apart nanowires of said first and second stacked nanowire structures; at least one work function adjusting metal layer positioned around said gate insulation layer and said outer perimeter of each nanowire of said plurality of vertically spaced-apart nanowires of said first and second stacked nanowire structures, wherein said at least one work function adjusting metal layer has an upper surface that is positioned above an upper surface of said layer of insulating material and above an uppermost nanowire of each of said first and second stacked nanowire structures; at least one conductive material positioned above said upper surface of said work function adjusting metal layer, wherein said at least one conductive material comprises a part of a gate structure for said nanowire device; and a gate cap layer positioned above said at least one conductive material.

19 . The nanowire device of claim 18 , further comprising:
a first epi semiconductor material positioned in a source/drain region of said nanowire device, said first epi semiconductor material having a first lateral width at an upper surface thereof; and a second epi semiconductor mater

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Taylor Jr William J
• Jacob Ajey Poovannummoottil

Classifications

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title