Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10204834-B2
Application number	US-201715655196-A
Country	US
Kind code	B2
Filing date	Jul 20, 2017
Priority date	Dec 9, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a first doping layer by implanting ions into an upper surface of a substrate;
forming a first channel layer on the first doping layer by an epitaxy method;
forming a second doping layer by implanting ions into an upper surface of the first channel layer;
forming a first junction region, a first channel region, and a second junction region, which are sequentially positioned on the substrate, by etching the first doping layer, the first channel layer, and the second doping layer, respectively;
forming a third junction region, a second channel region, and a fourth junction region, which are sequentially positioned on the substrate, by etching a third doping layer, a second channel layer, and a fourth doping layer, respectively, wherein the etching of the first doping layer comprises forming the first junction region so as to have a first portion and a second portion which has a smaller thickness than that of the first portion, and the etching of the third doping layer comprises forming the third junction region so as to have a third portion and a fourth portion which has a smaller thickness than that of the third portion; and
forming a first gate stack so as to at least partially surround the first channel region,
wherein the first doping layer and the second doping layer have a same conductivity type.

2. The method of claim 1 , further comprising:
forming a spacer positioned on the second portion of the first junction region and the fourth portion of the third junction region between the etching of the first doping layer and the forming of the first gate stack.

3. The method of claim 2 , wherein:
a height of the spacer is smaller than a height of the first channel region or the second channel region.

4. The method of claim 1 , further comprising:
forming a first contact auxiliary layer on the second junction region by using an epitaxy process; and
forming a second contact auxiliary layer on the fourth junction region by using the epitaxy process,
wherein the first contact auxiliary layer is formed to have a larger width than a width of the second junction region, and the second contact auxiliary layer is formed to have a larger width than a width of the fourth junction region.

5. The method of claim 1 , further comprising:
performing an annealing process comprising at least one of an operation between the forming of the first doping layer and the etching of the first doping layer, or an operation between the forming of the second doping layer and the etching of the second doping layer.

6. A method of fabricating a semiconductor device, the method comprising:
performing a device isolating process on a substrate;
forming a first doping layer in an n-type region and forming a third doping layer in a p-type region by implanting ions into respective portions of an upper surface of the substrate;
forming a first channel layer on the first doping layer in the n-type region and forming a second channel layer on the third doping layer in the p-type region by an epitaxy method;
forming a second doping layer on the first channel layer in the n-type region and forming a fourth doping layer on the second channel layer in the p-type region by implanting ions into respective upper surfaces thereof;
forming a first junction region, a first channel region, and a second junction region, which are sequentially positioned on the n-type region, by etching the first doping layer, the first channel layer, and the second doping layer, respectively;
forming a third junction region, a second channel region, and a fourth junction region, which are sequentially positioned on the p-type region, by etching the third doping layer, the second channel layer, and the fourth doping layer, respectively, in the etching of the first doping layer, the first channel layer, and the second doping layer;
forming a first gate stack so as to at least partially surround the first channel region; and
forming a second gate stack so as to at least partially surround the second channel region,
wherein the first doping layer and the second doping layer have a same conductivity type, and wherein the first channel layer and the second channel layer are simultaneously formed.

7. The method of claim 6 , wherein the epitaxy method is non-selective with respect to the first doping layer in the n-type region and the third doping layer in the p-type region.

8. A method of fabricating a semiconductor device, the method comprising:
forming an n-type transistor on a substrate, the n-type transistor comprising a first junction region, a first channel region on the first junction region, and a second junction region on the first channel region; and
forming a p-type transistor on the substrate adjacent the n-type transistor, the p-type transistor comprising a third junction region, a second channel region on the third junction region, and a fourth junction region on the second channel region,
wherein the first junction region has a first portion and a second portion which has a smaller thickness than that of the first portion, and the third junction region has a third portion and a fourth portion which has a smaller thickness than that of the third portion, and
wherein forming the n-type transistor and forming the p-type transistor comprises:
forming an epitaxial channel layer on the substrate and etching the epitaxial channel layer to simultaneously define the first channel region of the n-type transistor and the second channel region of the p-type transistor.

9. The method of claim 8 , wherein forming the n-type transistor and forming the p-type transistor further comprises:
forming a first doped layer and a third doped layer on the substrate by implanting ions into the substrate;
forming the epitaxial channel layer on the first and third doped layers by a non-selective epitaxy process;
forming a second doped layer and a fourth doped layer by implanting ions into surfaces of the epitaxial channel layer opposite the first doped layer and the third doped layer, respectively, wherein the first and second doped layers are n-type, and wherein the third and fourth doped layers are p-type;
sequentially etching the second and fourth doped layers, the epitaxial channel layer, and the first and third doped layers to define the second and fourth junction regions, the first and second channel regions, and the first and third junction regions; and
forming a first gate stack so as to at least partially surround the first channel region and a second gate stack so as to at least partially surround the second channel region.

10. The method of claim 8 , wherein the first portion is beneath the first channel region and the second portion laterally extends along the substrate beyond the first channel region, and wherein the third portion is beneath the second channel region and the fourth portion laterally extends along the substrate beyond the second channel region.

11. The method of claim 8 , further comprising:
forming a spacer on the second portion of the first junction region and the fourth portion of the third junction region.

12. The method of claim 8 , further comprising:
forming a first contact auxiliary layer on the second junction region and a second contact auxiliary layer on the fourth junction region,
wherein the first contact auxiliary layer has a larger width than that of the second junction region, and the second contact auxiliary layer has a larger width than that of the fourth junction region.

13. The method of claim 8 , wherein the first channel region and the second channe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Heo Yeon-Cheol

Classifications

• H01L21/823487 Primary

  Electricity · mapped topic

• H01L29/423

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L21/8238

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic