Chemical mechanical polishing slurry, method for chemical mechanical polishing and manufacturing method of semiconductor structure

Patent metadata

Field	Value
Publication number	US-10204793-B2
Application number	US-201615156867-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	May 17, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A chemical mechanical polishing (CMP) slurry, a method for CMP, and a manufacturing method of a semiconductor structure are provided. The CMP slurry includes a pH-adjustor for providing an alkaline environment in the CMP slurry and a silicon inhibitor for lowering a removal rate of silicon. The CMP slurry is used in a planarization operation to remove portions of a semiconductor region and portions of a silicon region. The semiconductor region comprises at least one semiconductor material different from silicon. The semiconductor region is formed in a recess adjacent to the silicon region. The particle defect condition may be improved by applying the alkaline CMP slurry, and the silicon inhibitor may be used to modify the removal rate selectivity between the semiconductor region and the silicon region in the planarization operation.

First claim

What is claimed is:

1. A method for chemical mechanical polishing (CMP), comprising:
receiving a substrate, wherein the substrate comprises a first well region of a first conductivity type, a second well region of a second conductivity type different from the first conductivity type and adjacent to the first well region, a silicon region over the first well region, a mask layer on the silicon region, and a semiconductor region adjacent to the silicon region, the semiconductor region comprising at least one semiconductor material different from silico;
performing a first planarization operation with a first slurry to remove the mask layer and a first portion of the semiconductor region; and
performing a second planarization operation with a second slurry different from the first slurry to remove a second portion of the semiconductor region and a portion of the silicon region.

2. The method of claim 1 , wherein the first slurry comprises:
a pH-adjustor; and
a silicon inhibitor.

3. The method of claim 2 , wherein the silicon inhibitor comprises an inhibitor lowering a removal rate of the silicon region in the planarization operation.

4. The method of claim 1 , wherein the first slurry has a selectivity, with the selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the silicon region, and the selectivity is higher than 0.6.

5. The method of claim 2 , wherein the silicon inhibitor comprises alkyl carboxylic acid, poly ethylene glycol, or polyoxyethylene alkyl ether.

6. The method of claim 2 , wherein a concentration of the silicon inhibitor in the first slurry is lower than or equal to 0.1% by weight.

7. The method of claim 2 , wherein the first slurry has a pH value greater than 7 and less than 12.

8. The method of claim 1 , wherein the mask layer comprises a dielectric material.

9. A method of manufacturing a semiconductor structure, the method comprising:
receiving a substrate, wherein the substrate comprises:
a first well region of a first conductivity type;
a second well region of a second conductivity type different from the first conductivity type and adjacent to the first well region;
a silicon region over the first well region and covering the second well region; and
a recess adjacent to the silicon region and over the second well region, the silicon region defining a bottom surface of the recess;

completely filling the recess with a semiconductor material different from silicon to form a semiconductor region in the recess; and
performing a chemical mechanical polishing (CMP) operation with an alkaline CMP slurry to the semiconductor region and the silicon region.

10. The manufacturing method of claim 9 , wherein the alkaline CMP slurry comprises:
a pH-adjustor; and
a silicon inhibitor configured to lower a removal rate of the silicon region in the CMP operation.

11. The manufacturing method of claim 9 , wherein the semiconductor region comprises a silicon germanium region.

12. A method of manufacturing a semiconductor structure, the method comprising:
receiving a substrate, wherein the substrate comprises;
a silicon region;
a first well region of a first conductivity type under the silicon region;
a second well region of a second conductivity type different from the first conductivity type adjacent to the first well region, the silicon region covering the second well region; and
a recess in the silicon region and aligned with the second well region,
wherein the substrate further comprises a mask layer covering an entirety of the silicon region;

completely filling the recess with a semiconductor material different from silicon to form a semiconductor region in the recess; and
removing an entirety of the mask layer, a portion of the semiconductor region and a portion of the silicon region with an alkaline chemical mechanical polishing (CMP) slurry comprising a silicon inhibitor.

13. The method of claim 12 , wherein the silicon inhibitor comprises alkyl carboxylic acid, poly ethylene glycol, or polyoxyethylene alkyl ether.

14. The method of claim 13 , wherein the polyoxyethylene alkyl ether comprises polyoxyethylene lauryl ether or polyoxyethylene tridecyl ether.

15. The method of claim 12 , wherein the alkaline CMP slurry has a selectivity, with the selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the silicon region, and the selectivity is between 1 and 4.

16. The method of claim 12 , wherein a concentration of the silicon inhibitor in the alkaline CMP slurry is lower than or equal to 0.1% by weight.

17. The method of claim 12 , wherein the alkaline CMP slurry has a pH value between 8 and 10.

18. The method of claim 12 , wherein the alkaline CMP slurry further comprises a pH adjustor comprising at least one of ammonium hydroxide (NH 4 OH) and quaternary ammonium hydroxide salt.

19. The method of claim 12 , further comprising forming a cap layer over the semiconductor region and the silicon region subsequent to the polishing operation.

20. The method of claim 12 , prior to the polishing operation with the alkaline CMP slurry, further comprising performing a CMP operation on the semiconductor region and the silicon region with an acidic slurry.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Shu-Hao

Classifications

• H10P52/402 Primary

  of semiconductor materials · CPC title

• C09G1/02

  containing abrasives or grinding agents {(abrasives as such C09K3/14; polishing of semi-conductors H10P52/40)} · CPC title

• C09G1/04

  Aqueous dispersions (C09G1/02 takes precedence) · CPC title

• B24B37/11 Primary

  Lapping tools · CPC title

• H01L21/30625 Primary

  Electricity · mapped topic