Self-aligned punch through stopper liner for bulk FinFET

Patent metadata

Field	Value
Publication number	US-9559014-B1
Application number	US-201514950583-A
Country	US
Kind code	B1
Filing date	Nov 24, 2015
Priority date	Sep 4, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

First claim

What is claimed is:

1. A method of making a self-aligned field effect transistor structure, the method comprising:
providing a starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region having a boron doped layer deposited over at least one of the plurality of fins, a p-type field effect transistor (PFET) region having a phosphorous or arsenic doped layer deposited over at least one of the plurality of fins, and a center region having a boundary defect at the interface of the NFET region having the boron doped layer deposited thereon and the PFET region having the phosphorous or arsenic doped layer deposited thereon;
masking the NFET region having the boron doped layer deposited thereon and the PFET region having a phosphorous doped layer deposited thereon such that the center region is exposed;
etching the center boundary region to remove the boundary defect, wherein etching the center boundary region comprises using a timed etch to remove at least one fin present in the center region such that the timed etch stops at an upper most surface of the substrate;
removing the mask covering the NFET region having the boron doped layer deposited thereon and the PFET region having a phosphorous doped layer;
filling the etched center boundary region with an insulator material;
planarizing the punch through stopper having the center boundary region filled with the insulator material;
revealing a portion of the plurality of fins patterned in the substrate such that at least a portion of the boron doped layer adjacent to the fins forming the NFET region and at least a portion of the phosphorous or arsenic doped layer adjacent to the fins forming the PFET region is revealed; and
doping a portion of the fins and substrate that is adjacent to the boron doped layer with boron type dopants and doping a portion of the fins and substrate that are adjacent to the phosphorous or arsenic doped layer with phosphorous or arsenic type dopants.

2. The method of claim 1 , wherein etching the center boundary region comprises using a timed etch to remove at least one fin present in the center region such that the timed etch stops just below an upper most surface of the substrate.

3. The method of claim 1 , wherein etching the center boundary region comprises using a reactive ion etching process.

4. The method of claim 1 , wherein etching the center boundary region comprises using a directional reactive ion etching process.

5. The method of claim 1 , wherein doping a portion of the fins and substrate that is adjacent to the boron doped layer with boron type dopants and doping a portion of the fins and substrate that are adjacent to the phosphorous or arsenic doped layer with phosphorous or arsenic type dopants, comprises annealing the punch through stopper structure.

6. The method of claim 1 , further comprising forming at least one gate on the punch through stopper structure.

Assignees

• IBM

Inventors

• Basker Veeraraghavan
• Cheng Kangguo
• Standaert Theodorus
• Wang Junli

Classifications

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title