Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

Patent metadata

Field	Value
Publication number	US-10199294-B1
Application number	US-201816024856-A
Country	US
Kind code	B1
Filing date	Jun 30, 2018
Priority date	Feb 3, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

First claim

What we claim in this application is:

1. A method for processing a semiconductor wafer, comprising at least the following acts:
patterning a multiplicity of library-compatible cells on the wafer, wherein each library-compatible cell includes:
(i) first and second elongated conductive supply rails that extend horizontally across an entire width of the cell, where the first and second supply rails are configured for compatibility with corresponding supply rails contained in other library-compatible cells; and
(ii) multiple gate stripes that extend vertically between the cell's first and second supply rails, with the gate stripes spaced horizontally at a pitch (CPP) that is consistent with other library-compatible cells;

said patterning of said multiplicity of library-compatible cells including:
(i) patterning a first library-compatible cell that includes a side-to-side short-configured test area;
(ii) patterning a second library-compatible cell that includes a via-chamfer short-configured test area; and
(iii) patterning a third library-compatible cell that includes a corner short-configured test area;

using a charged particle-beam inspector to obtain one or more first inline non-contact electrical measurements (inline NCEMs) from the first library-compatible cell, where each first inline NCEM provides a measurement indicative of a short or leakage in the side-to-side short-configured test area of the cell, said one or more measurements obtained by:
(i) moving a stage in the inspector while scanning a conductive feature associated with the first library-compatible cell; and
(ii) deflecting the inspector's charged particle-beam to account for motion of the stage during the scanning of the feature;

using the charged particle-beam inspector to obtain one or more second inline NCEMs from the second library-compatible cell, where each second inline NCEM provides a measurement indicative of a short or leakage in the via-chamfer short-configured test area of the cell, said one or more measurements obtained by:
(i) moving the stage in the inspector while scanning a conductive feature associated with the second library-compatible cell; and
(ii) deflecting the inspector's charged particle-beam to account for motion of the stage during the scanning of the feature;

using the charged particle-beam inspector to obtain one or more third inline NCEMs from the third library-compatible cell, where each third inline NCEM provides a measurement indicative of a short or leakage in the corner short-configured test area of the cell, said one or more measurements obtained by:
(i) moving the stage in the inspector while scanning a conductive feature associated with the third library-compatible cell; and
(ii) deflecting the inspector's charged particle-beam to account for motion of the stage during the scanning of the feature.

2. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional metrology steps in the continued processing of the wafer or other wafers currently being manufactured.

3. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional inspection steps in the continued processing of the wafer or other wafers currently being manufactured.

4. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional processing steps in the continued processing of the wafer or other wafers currently being manufactured.

5. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more metrology steps in the continued processing of the wafer or other wafers currently being manufactured.

6. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more inspection steps in the continued processing of the wafer or other wafers currently being manufactured.

7. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more processing steps in the continued processing of the wafer or other wafers currently being manufactured.

8. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to continue or abandon processing of the wafer.

9. A method for processing, as defined in claim 1 , wherein:
patterning the first library-compatible cell further comprises:
(i) patterning a first non-contact electrical measurement (NCEM) pad; and
(ii) connecting the first NCEM pad to a first portion of the cell's side-to-side short-configured test area;

patterning the second library-compatible cell further comprises:
(i) patterning a second NCEM pad; and
(ii) connecting the second NCEM pad to a first portion of the cell's via-chamfer short-configured test area; and

patterning the third library-compatible cell further comprises:
(i) patterning a third NCEM pad; and
(ii) connecting the third NCEM pad to a first portion of the cell's corner short-configured test area.

10. A method for processing, as defined in claim 9 , wherein:
patterning the first library-compatible cell further comprises connecting a second portion of the cell's side-to-side short-configured test area to a virtually grounded structure;
patterning the second library-compatible cell further comprises connecting a second portion of the cell's via-chamfer short-configured test area to a virtually grounded structure; and
patterning the third library-compatible cell further comprises connecting a second portion of the cell's corner short-configured test area to a virtually grounded structure.

11. A method for processing, as defined in claim 9 , wherein:
patterning the first library-compatible cell further comprises connecting a second portion of the cell's side-to-side short-configured test area to one of the cell's supply rails;
patterning the second library-compatible cell further comprises connecting a second portion of the cell's via-chamfer short-configured test area to one of the cell's supply rails; and
patterning the third library-compatible cell further comprises connecting a second portion of the cell's corner short-configured test area to one of the cell's supply rails.

12. A method for processing, as defined in claim 9 , wherein the first, second, and third NCEM pads are square, and obtaining each inline NCEM utilizes a charged particle-beam with a square spot designed to match a footprint of the NCEM pad.

13. A method for processing, as defined in claim 9 , wherein the first, second, and third NCEM pads each have an aspect ratio of greater than 3, and obtaining each inline NCEM utilizes a charged particle-beam with a line-shaped spot.

14. A method for processing, as defined in claim 9 , wherein obtaining the first, second, and third inline NCEMs involves selectively targeting the first, second, and third NCEM pads, respectively.

15. A method for processing, as defined in claim 9 , wherein each of the first, second, and third NCEM pads is patterned within a scribe line area of the wafer.

16. A method for processing, as defined in claim 9 , wherein each of the first, second, and third NCEM pads is patterned within a standard cell logic block.

Assignees

• Pdf Solutions Inc

Inventors

• Lam Stephen
• Ciplickas Dennis
• Brozek Tomasz
• Cheng Jeremy
• Comensoli Simone
• De Indranil
• Doong Kelvin
• Eisenmann Hans
• Fiscus Timothy
• Haigh Jonathan
• Hess Christopher
• Kibarian John
• Lee Sherry
• Liao Marci
• Lin Sheng-Che
• Matsuhashi Hideki
• Michaels Kimon
• O'Sullivan Conor
• Rauscher Markus
• Rovner Vyacheslav
• Strojwas Andrzej
• Strojwas Marcin
• Taylor Carl
• Vallishayee Rakesh
• Weiland Larg
• Yokoyama Nobuharu

Classifications

• G01R31/307

  of integrated circuits · CPC title

• G01R31/2831

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/30

  Circuit design · CPC title