Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas

Patent metadata

Field	Value
Publication number	US-10199288-B1
Application number	US-201815942483-A
Country	US
Kind code	B1
Filing date	Mar 31, 2018
Priority date	Feb 3, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.

First claim

What we claim in this application is:

1. A method for processing a semiconductor wafer, comprising at least the following acts:
patterning a side-to-side short-configured test area on the wafer;
patterning a first non-contact electrical measurement (NCEM) pad on the wafer;
patterning one or more connections to (i) electrically connect a first portion of the side-to-side short-configured test area to the first NCEM pad and (ii) electrically connect a second portion of the side-to-side short-configured test area to a permanent or virtual ground;
patterning a corner short-configured test area on the wafer;
patterning a second NCEM pad on the wafer;
patterning one or more connections to (i) electrically connect a first portion of the corner short-configured test area to the second NCEM pad and (ii) electrically connect a second portion of the corner short-configured test area to a permanent or virtual ground;
patterning a via open-configured test area on the wafer;
patterning a third NCEM pad on the wafer;
patterning one or more connections to (i) electrically connect a first portion of the via open-configured test area to the third NCEM pad and (ii) electrically connect a second portion of the via open-configured test area to a permanent or virtual ground;
obtaining one or more first inline non-contact electrical measurements (inline NCEMs) from the first NCEM pad, where each first inline NCEM provides a measurement indicative of a short or leakage in the side-to-side short-configured test area;
obtaining one or more second inline NCEMs from the second NCEM pad, where each second inline NCEM provides a measurement indicative of a short or leakage in the corner short-configured test area; and,
obtaining one or more third inline NCEMs from the third NCEM pad, where each third inline NCEM provides a measurement indicative of an open or resistance in the via open-configured test area.

2. A method for processing, as defined in claim 1 , wherein obtaining the first, second, and third inline NCEMs involves using an e-beam inspector to obtain the NCEMs from the respective NCEM pads, by:
moving a stage in the inspector while scanning the respective NCEM pad; and,
deflecting the inspector's e-beam to account for motion of the stage during the scanning of the respective NCEM pad.

3. A method for processing, as defined in claim 1 , wherein the acts of patterning the corner short-configured test area, patterning the second NCEM pad, and patterning the connections from/to the corner short-configured test area and the second NCEM pad are accomplished by instantiating a corner-short-configured or corner-leakage-configured, NCEM-enabled fill cell on the wafer.

4. A method for processing, as defined in claim 1 , wherein the acts of patterning the via open-configured test area, patterning the third NCEM pad, and patterning the connections from/to the via open-configured test area and the third NCEM pad are accomplished by instantiating a via-open-configured or via-resistance-configured, NCEM-enabled fill cell on the wafer.

5. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional processing steps in the continued processing of the wafer or other wafers currently being manufactured.

6. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional inspection steps in the continued processing of the wafer or other wafers currently being manufactured.

7. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional metrology steps in the continued processing of the wafer or other wafers currently being manufactured.

8. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more processing steps in the continued processing of the wafer or other wafers currently being manufactured.

9. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more inspection steps in the continued processing of the wafer or other wafers currently being manufactured.

10. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more metrology steps in the continued processing of the wafer or other wafers currently being manufactured.

11. A method for processing, as defined in claim 1 , wherein the first, second, and third NCEM pads are square, and obtaining each inline NCEM utilizes an e-beam with a square spot designed to match a footprint of the NCEM pads.

12. A method for processing, as defined in claim 1 , wherein the first, second, and third NCEM pads each have an aspect ratio of greater than 3, and obtaining each inline NCEM utilizes an e-beam with a line-shaped spot.

13. A method for processing, as defined in claim 1 , further comprising using the first, second, and third inline NCEMs to determine whether to continue or abandon processing of the wafer.

14. A method for processing, as defined in claim 1 , wherein each of the first, second, and third NCEM pads is patterned within a scribe line area of the wafer.

15. A method for processing, as defined in claim 1 , wherein each of the first, second, and third NCEM pads is patterned within a standard cell logic block.

16. A method for processing, as defined in claim 1 , wherein the acts of patterning the side-to-side short-configured test area, patterning the first NCEM pad, and patterning the connections from/to the side-to-side short-configured test area and the first NCEM pad are accomplished by instantiating a side-to-side-short-configured or side-to-side-leakage-configured, NCEM-enabled fill cell on the wafer.

17. A method for processing, as defined in claim 16 , that further comprises instantiating additional, differently configured, NCEM-enabled fill cells, said differently configured fill cells selected from a list that consists of:
tip-to-tip-short-configured, NCEM-enabled fill cells;
tip-to-tip-leakage-configured, NCEM-enabled fill cells;
tip-to-side-short-configured, NCEM-enabled fill cells;
tip-to-side-leakage-configured, NCEM-enabled fill cells;
side-to-side-short-configured, NCEM-enabled fill cells;
side-to-side-leakage-configured, NCEM-enabled fill cells;
L-shape-interlayer-short-configured, NCEM-enabled fill cells;
L-shape-interlayer-leakage-configured, NCEM-enabled fill cells;
diagonal-short-configured, NCEM-enabled fill cells;
diagonal-leakage-configured, NCEM-enabled fill cells;
corner-short-configured, NCEM-enabled fill cells;
corner-leakage-configured, NCEM-enabled fill cells;
interlayer-overlap-short-configured, NCEM-enabled fill cells;
interlayer-overlap-leakage-configured, NCEM-enabled fill cells;
via-chamfer-short-configured, NCEM-enabled fill cells;
via-chamfer-leakage-configured, NCEM-enabled fill cells;
merged-via-short-configured, NCEM-enabled fill cells;
merged-via-leakage-configured, NCEM-enabled fill cells;
snake-open-configured, NCEM-enabled fill cells;
snake-resistance-configured, NCEM-enabled fill cells;
stitch-open-configured, NCEM-enabled fill cells;
stitch-resistance-configured, NCEM-enabled fill cells;
via-open-configured, NCEM-enabled fill cells;
via-resistance-configure

Assignees

• Pdf Solutions Inc

Inventors

• Lam Stephen
• Ciplickas Dennis
• Brozek Tomasz
• Cheng Jeremy
• Comensoli Simone
• De Indranil
• Doong Kelvin
• Eisenmann Hans
• Fiscus Timothy
• Haigh Jonathan
• Hess Christopher
• Kibarian John
• Lee Sherry
• Liao Marci
• Lin Sheng-Che
• Matsuhashi Hideki
• Michaels Kimon
• O'Sullivan Conor
• Rauscher Markus
• Rovner Vyacheslav
• Strojwas Andrzej
• Strojwas Marcin
• Taylor Carl
• Vallishayee Rakesh
• Weiland Larg
• Yokoyama Nobuharu

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title