Methods and apparatuses for electroplating and seed layer detection

Patent metadata

Field	Value
Publication number	US-10196753-B2
Application number	US-201715782690-A
Country	US
Kind code	B2
Filing date	Oct 12, 2017
Priority date	Jan 21, 2014
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

Disclosed herein are methods and apparatuses for electroplating which employ seed layer detection. Such methods and related apparatuses may operate by selecting a wafer for processing, measuring from its surface one or more in-process color signals having one or more color components, calculating one or more metrics, each metric indicative of the difference between one of the in-process color signals and a corresponding set of reference color signals, determining whether an acceptable seed layer is present on the wafer surface based on whether a predetermined number of the one or more metrics are within an associated predetermined range which individually corresponds to that metric, and either electroplating the wafer when an acceptable seed layer is present or otherwise designating the wafer unacceptable for electroplating. The foregoing may then be repeated for one or more additional wafers to electroplate multiple wafers from a set of wafers.

First claim

We claim:

1. A system comprising:
a seed layer analysis system that includes an illumination source and a color sensor; and
a system controller configured to:
(a) cause a wafer from a set of semiconductor wafers to be selected,
(b) cause, after (a), the illumination source to illuminate one or more points within an interior region of a surface of the selected wafer, and the color sensor to measure a first set of one or more in-process color signals from the one or more points within the interior region of the surface of the selected wafer, each color signal having one or more color components,
(c) cause, after (a), the illumination source to illuminate one or more points within an edge region of the surface of the selected wafer, and the color sensor to measure a second set of one or more in-process color signals from the one or more points within the edge region of the surface of the selected wafer, each color signal having one or more color components,
(d) calculate, after (b) and (c), a metric indicative of the difference between the color signals in the first and second sets of in-process color signals, and
(e) determine whether an acceptable seed layer is present on the surface of the selected wafer based on whether the metric is within a predetermined range.

2. The system of claim 1 , further comprising:
one or more wafer storage devices for storing, loading, and unloading wafers; and
a robotic wafer transfer mechanism configured to transfer wafers to and from at least one of wafer storage devices and/or the seed layer analysis system, wherein:
the system controller is further configured in (a) to cause the robotic wafer transfer mechanism to select a wafer from the one or more wafer storage devices, and
the system controller is further configured to cause the robotic wafer transfer mechanism to position the selected wafer for illumination by the illumination source.

3. The system of claim 2 , further comprising an electroplating module configured to electroplate a plurality of wafers from the set of semiconductor wafers, wherein the system controller is further configured to:
(f) cause, based on the determination in (e), the electroplating module to electroplate the selected wafer when an acceptable seed layer is present on the selected wafer,
(g) cause, based on the determination in (e), the selected wafer to be designated as not acceptable for electroplating when an acceptable seed layer is not present,
cause, based on (e) and before (f), the robotic wafer transfer mechanism to transfer the selected wafer to the electroplating module for electroplating, and
cause, based on (g), the robotic wafer transfer mechanism to transfer the selected wafer a rejected wafer storage area configured to store rejected wafers.

4. The system of claim 1 , further comprising an electroplating module configured to electroplate a plurality of wafers from the set of semiconductor wafers, wherein system controller is further configured to:
(f) cause, based on the determination in (e), the electroplating module to electroplate the selected wafer when an acceptable seed layer is present on the selected wafer, and
(g) cause, based on the determination in (e), the selected wafer to be designated as not acceptable for electroplating when an acceptable seed layer is not present.

5. The system of claim 1 , wherein:
the illumination source comprises a first illumination source and a second illumination source,
the color sensor comprises a first color sensor and a second color sensor,
the system controller is further configured in (b) to cause the first illumination source to illuminate one or more points within the interior region of the surface of the selected wafer, and the first color sensor to measure the first set of one or more in-process color signals from the one or more points within the interior region of the surface of the selected wafer, and
the system controller is further configured in (c) to cause the second illumination source to illuminate one or more points within the edge region of the surface of the selected wafer, and the second color sensor to measure the second set of one or more in-process color signals from the one or more points within the edge region of the surface of the selected wafer.

6. The system of claim 1 , wherein the locations of the points on the surface of the selected wafer at which the first and second sets of color signals are measured are a fixed set of azimuthal and radial positions relative to the edge of the selected wafer and an alignment notch of the selected wafer.

7. The system of claim 1 , wherein the metric is indicative of the magnitude of the vector difference between:
the vector average of the first set of one or more in-process color signals; and
the vector average of the second set of one or more in-process color signals.

8. The system of claim 1 , wherein the one or more color components of the color signals of the first and second sets comprise a first color component whose value is indicative of the relative proportion of green versus red in the color signals.

9. The system of claim 1 , wherein the one or more color components of the color signals of the first and second sets comprise a first color component whose value is indicative of the relative proportion of blue versus yellow in the color signals.

10. The system of claim 1 , wherein:
the illumination source is configured to emit substantially white light,
the illumination in (b) further comprises causing the illumination source to illuminate the one or more points within the interior region of the surface of the selected wafer with substantially white light to reflect light from the interior region, and
the illumination in (c) further comprises causing the illumination source to illuminate one or more points within the edge region of the surface of the selected wafer with substantially white light to reflect light from the edge region.

11. The system of claim 1 , wherein the system controller is further configured to randomly choose the locations of the points on the surfaces of the wafers at which the first and second sets of color signals are measured.

12. The system of claim 1 , further comprising a physical vapor deposition (PVD) tool for depositing a seed layer, wherein the system controller is further configured to cause, before (a), the PVD tool to deposit a seed layer on each of the wafers in the set of semiconductor wafers.

13. The system of claim 1 , wherein the acceptable seed layer is a copper seed layer.

14. The system of claim 13 , wherein the acceptable seed layer is a copper seed layer having a thickness of less than about 200 angstroms.

15. The system of claim 14 , wherein the acceptable seed layer is a copper seed layer having a thickness of between about 50 and 150 angstroms.

16. The system of claim 14 , wherein the electroplating module comprises:
a cell for containing an anode and electroplating solution during electroplating,
a wafer holder for holding and rotating a wafer during electroplating, and
a power supply for supplying current to the wafer during electroplating.

17. The system of claim 1 , wherein:
the first set of one or more in-process color signals in (b) includes a first color signal and a second color signal,
the second set of one or more in-process color signals in (c) includes a third color signal and a fourth color signal,
the system controller is further configured in (d) to calculate a first metric indicative of the difference between the first color signal and the third color signal, and to calculate

Assignees

• Lam Res Corp

Inventors

• Dinneen Daniel Mark
• Mayer Steven T

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P72/04

  Apparatus for manufacture or treatment · CPC title

• C25D17/16 Primary

  Apparatus for electrolytic coating of small objects in bulk · CPC title

• C25D7/123 Primary

  Semiconductors first coated with a seed layer or a conductive layer · CPC title

• C25D17/001

  Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells · CPC title