Engineering change order (ECO) cell, layout thereof and integrated circuit including the ECO cell

Patent metadata

Field	Value
Publication number	US-10192860-B2
Application number	US-201615236654-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Oct 26, 2015
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

An engineering change order (ECO) base cell and an integrated circuit (IC) including the ECO base cell are provided. The IC includes a plurality of standard cells and at least one engineering change order (ECO) base cell. The ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
an integrated circuit substrate;
a plurality of standard cells on said integrated circuit substrate; and
at least one engineering change order (ECO) base cell on the integrated circuit substrate;
wherein the ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates having different logic configurations relative to each other;
wherein the layout of the ECO base cell includes a plurality of spaced-apart and dissimilar regions that are each associated with a respective one of the plurality of logic gates, with each of the plurality of dissimilar regions comprising a plurality of spaced-apart active regions and a plurality of gate lines overlapping the plurality of spaced-apart active regions; and
wherein the plurality of gate lines are disposed asymmetrically on said integrated circuit substrate so that the gate lines within at least two of the plurality of dissimilar regions lack symmetry relative to each other and relative to an axis extending between the at least two of the plurality of dissimilar regions.

2. The IC of claim 1 , wherein the ECO base cell has a layout obtained by removing a metal layer and/or a via connected to the metal layer from the layout of the functional cell corresponding to the first circuit.

3. The IC of claim 1 , wherein the layout of the ECO base cell comprises at least three gate lines that are parallel to one another.

4. The IC of claim 1 , further comprising an ECO functional cell having a layout obtained by adding a pattern of a metal layer and a via connected to the pattern to the layout of the ECO base cell.

5. The IC of claim 4 , wherein the ECO functional cell corresponds to a second circuit including at least one of the plurality of logic gates.

6. The IC of claim 5 , wherein the second circuit is identical with the first circuit.

7. The IC of claim 5 , wherein the second circuit comprises at least two logic gates, wherein the second circuit comprises first and second subcircuits, each of which comprises at least one of the at least two logic gates, and
the first and second subcircuits are insulated from each other in the ECO functional cell.

8. The IC of claim 1 , wherein the ECO base cell is a filler cell or a decoupling capacitor cell placed in a spare region of a layout of the IC.

9. The IC of claim 1 , wherein the functional cell is a standard cell.

10. An integrated circuit device, comprising:
a plurality of interconnected standard logic cells distributed within a standard cell region on an integrated circuit substrate; and
at least a first engineering change order (ECO) base cell within a spare region of the substrate extending adjacent the standard cell region, said first ECO base cell comprising a plurality of logic cells and having an in-substrate layout corresponding to an in-substrate layout of a functional logic cell and an above-substrate layout that is incomplete relative to an above-substrate layout of the functional logic cell;
wherein the at least a first ECO base cell includes a plurality of spaced-apart and dissimilar regions that are each associated with a respective one of the plurality of logic gates, with each of the plurality of dissimilar regions comprising a plurality of spaced-apart active regions and a plurality of gate lines overlapping the plurality of spaced-apart active regions; and
wherein the plurality of gate lines are disposed asymmetrically on the integrated circuit substrate so that the gate lines within at least two of the plurality of dissimilar regions lack symmetry relative to each other and relative to an axis extending between the at least two of the plurality of dissimilar regions.

11. The device of claim 10 , wherein the above-substrate layout of said first ECO base cell is missing at least one electrically conductive via and/or at least one metal interconnect relative to the above-substrate layout of the functional logic cell.

12. The device of claim 11 , wherein said first ECO base cell is configured to be functionally and layout equivalent to the functional logic cell upon addition of the missing at least one electrically conductive via and/or the at least one metal interconnect to said first ECO base cell.

13. The device of claim 10 , wherein said first ECO base cell is configured to comprise a decoupling capacitor.

14. The device of claim 11 , wherein the functional logic cell is equivalent to a standard logic cell in said plurality of interconnected standard logic cells.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Jae-Woo
• Lee Dal-Hee

Classifications

• G06F30/23

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/118

  Electricity · mapped topic

• G06F17/5068

  Physics · mapped topic