Component and method of manufacturing a component using an ultrathin carrier

Patent metadata

Field	Value
Publication number	US-10186458-B2
Application number	US-201213542655-A
Country	US
Kind code	B2
Filing date	Jul 5, 2012
Priority date	Jul 5, 2012
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

First claim

What is claimed is:

1. A method for manufacturing a plurality of components, the method comprising:
mounting a carrier comprising a semiconductor substrate on a supporting glass carrier;
processing the carrier to form a plurality of functional components, the plurality of functional components being separated from each other by kerf regions;
after forming the kerf regions and the plurality of functional components, forming a metal pattern comprising a metal on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions, wherein regions substantially vertically above the kerf region are free from the metal;
removing the supporting glass carrier from the carrier; and
separating the carrier into the plurality of components after removing the supporting glass carrier from the carrier,
wherein a thickness of the carrier and a thickness of the metal pattern comprise substantially the same thickness, or wherein the thickness of the carrier is smaller than the thickness of the metal pattern, and
wherein forming the metal pattern comprises forming a metal seed layer, forming an under-layer between the seed layer and the carrier, wherein the under-layer comprises a metal adhesion layer and a metal barrier layer, forming a patterned resist mask, and electro-plating the metal pattern.

2. The method according to claim 1 , wherein the metal pattern comprises copper (Cu).

3. The method according to claim 1 , wherein a thickness of the carrier is about 20 μm or less, and wherein a thickness of the metal pattern is about 20 μm or more.

4. The method according to claim 1 , wherein separating the carrier into the plurality of components comprises laser cutting the carrier along the regions.

5. A technique for manufacturing a plurality of components, the method comprising:
mounting a carrier comprising a semiconductor substrate on a support carrier;
processing the carrier to form a plurality of functional components and kerf regions, wherein the plurality of functional components are separated from each other by the kerf regions, wherein each of the plurality of functional components comprises a discrete device or an integrated circuit;
after forming the kerf regions and the plurality of functional components, forming a metal pattern comprising a metal on a backside of the carrier, wherein the metal pattern comprises free standing metal blocks, wherein the metal pattern is separated by spaces, and wherein each metal block covers substantially an entire backside area of each functional component, wherein regions substantially vertically above the kerf region are free from the metal, wherein forming the metal pattern comprises:
forming a metal seed layer;
forming a patterned resist mask; and
plating the metal pattern;

forming an under-layer between the metal seed layer and the carrier, wherein the under-layer comprises a metal layer stack of aluminum and titanium, and wherein the metal seed layer comprises the same material as the metal pattern;
removing the support carrier from the carrier; and
separating the carrier into the plurality of components along the spaces after the removing.

6. The method according to claim 5 , wherein the carrier comprises a thickness of about 20 μm or less, and wherein the metal pattern comprises a thickness of about 20 μm or more.

7. The method according to claim 6 , wherein separating the carrier into the plurality of components comprises laser cutting the carrier.

8. The method according to claim 6 , further comprising placing a component of the plurality of components on a leadframe, and encapsulating the component and at least a portion of the leadframe.

9. The method according to claim 8 , wherein placing the component on the leadframe comprises wire bonding or clip bonding the component to the leadframe.

10. The method according to claim 5 , wherein a thickness of the carrier and a thickness of the metal pattern are substantially equal or wherein the thickness of the carrier is smaller than the thickness of the metal pattern.

11. A method comprising:
mounting a wafer comprising a semiconductor substrate on a support carrier;
processing the wafer to form kerf regions and chips, wherein the chips are separated from each other by the kerf regions, wherein each chip comprises a discrete device or an integrated circuit, wherein the processing comprises thinning to expose a back surface, the wafer after the thinning having a front surface and the back surface;
after forming the kerf regions and the chips, forming a metal pattern comprising a metal on the back surface of the wafer, wherein the metal pattern covers the back surface of the wafer except over regions substantially vertically above the kerf regions, wherein regions substantially vertically above the kerf region are free from the metal; and
separating the wafer from the support carrier,
wherein forming the metal pattern comprises forming a seed layer, and forming an under-layer between the seed layer and the back surface of the wafer, the under-layer including a metal adhesion layer and a metal barrier layer.

12. The method according to claim 11 , wherein the metal pattern comprises copper (Cu).

13. The method according to claim 11 , wherein forming the metal pattern further comprises:
patterning a photoresist over the seed layer; and
forming the metal pattern in a metal bath.

14. The method according to claim 11 , wherein a thickness of the wafer and a thickness of the metal pattern are substantially equal or wherein the thickness of the wafer is smaller than the thickness of the metal pattern.

15. A method comprising:
processing a wafer to form kerf regions and chips, wherein the chips are separated from each other by the kerf regions, wherein each chip comprises a discrete device or an integrated circuit, and wherein the wafer comprises a front surface and a back surface;
thinning the wafer on the back surface;
after forming the kerf regions and the chips, forming a metal pattern comprising a metal on the back surface of the wafer, wherein regions substantially vertically above the kerf regions are free from the metal, wherein a thickness of the wafer and a thickness of the metal pattern are substantially equal or wherein the thickness of the wafer is smaller than the thickness of the metal pattern, and wherein forming the metal pattern comprises forming a seed layer, forming an under-layer between the seed layer and the back surface of the wafer, the under-layer including a metal adhesion layer and a metal barrier layer, patterning a photoresist over the seed layer, and forming the metal pattern in a metal bath; and
separating the wafer into the chips.

16. The method according to claim 15 , wherein the discrete device comprises a transistors, a thyristor or a diode.

17. The method according to claim 15 ,
wherein the thickness of the wafer is smaller than the thickness of the metal pattern.

18. The method according to claim 15 , wherein a thickness of the wafer and a thickness of the metal pattern are substantially equal.

Assignees

• Mayer Karl
• Napetschnig Evelyn
• Pinczolits Michael
• Sternad Michael
• Roesner Michael
• Infineon Technologies Ag

Inventors

• Mayer Karl
• Napetschnig Evelyn
• Pinczolits Michael
• Sternad Michael
• Roesner Michael

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/886

  Die-attach connectors and strap connectors · CPC title

• H10W72/07636

  Soldering or alloying · CPC title