Mechanisms for forming patterns using multiple lithography processes
US-9875906-B2 · Jan 23, 2018 · US
Dummy pattern addition to improve CD uniformity
US10170309B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10170309-B2 |
| Application number | US-201715422689-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 15, 2017 |
| Priority date | Feb 15, 2017 |
| Publication date | Jan 1, 2019 |
| Grant date | Jan 1, 2019 |
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Abstract
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A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an existing masking layer and thus does not alter the printed image, improves the critical dimension uniformity (CDU) of main critical (non-dummy) features at the same masking level.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor device, comprising: forming a first masking layer over a semiconductor substrate, the first masking layer comprising first features; and forming a second masking layer over the semiconductor substrate, the second masking layer comprising second features, wherein a first portion of the first features are formed laterally adjacent to the second features, a second portion of the first features entirely overlie the second features, a first portion of the second features are formed laterally adjacent to the first features, and a second portion of the second features entirely overlie the first features, wherein the first features have a constant width and the second features have a constant width different from the width of the first features, and wherein the semiconductor device comprises an SRAM. 2. The method of claim 1 , wherein the second masking layer is formed after forming the first masking layer. 3. The method of claim 1 , wherein the first features of the first masking layer are arranged at an inter-feature spacing of 25 to 75 nm. 4. The method of claim 1 , wherein the second features of the second masking layer are arranged at an inter-feature spacing of 25 to 75 nm. 5. The method of claim 1 , wherein the second features of the second masking layer are arranged at a constant inter-feature spacing of 25 to 75 nm.
Assignees
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Classifications
- H10P76/408Primary
characterised by their sizes, orientations, dispositions, behaviours or shapes · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L21/0337Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US10170309B2 cover?
- A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an existing masking layer and thus does not alter the printed image, improves the critical dimension uniformity (CDU) of main critical (non-dummy) features at the same masking level.
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P76/408. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).