Patterning assist feature to mitigate reactive ion etch microloading effect

Patent metadata

Field	Value
Publication number	US-9252022-B1
Application number	US-201414533629-A
Country	US
Kind code	B1
Filing date	Nov 5, 2014
Priority date	Nov 5, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of fabricating a semiconductor device includes forming a masking layer on an upper surface of a semiconductor substrate. The masking layer is patterned to form at least one masking element that designates an active region of the semiconductor substrate and at least one patterning assist feature adjacent the at least one masking element. An etching process is performed to form a plurality of semiconductor fins on the semiconductor substrate. The plurality of semiconductor fins include at least one isolated fin formed on the active region according to the at least one masking element and at least one sacrificial fin formed according to the patterning assist feature that reduces a loading effect that occurs during the etching process.

First claim

The invention claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a masking layer on an upper surface of a semiconductor substrate;
patterning the masking layer to form at least one masking element that designates an active region of the semiconductor substrate and at least one patterning assist feature adjacent the at least one masking element; and
performing an etching process to form a plurality of semiconductor fins on the semiconductor substrate, the plurality of semiconductor fins including at least one isolated fin formed on the active region according to the at least one masking element and at least one sacrificial fin formed according to the at least one patterning assist feature that reduces a loading effect that occurs during the etching process,
wherein the etching process is a reactive ion etching (RIE) process, and wherein the at least one patterning assist feature realizes diffusion of reactive neutral species generated by the RIE process such that passivation to the sidewalls of the at least one isolated fin is reduced.

2. The method of claim 1 , further comprising:
after performing the etching process, forming at least one first cut mask on the upper surface of the semiconductor substrate to cover at least one portion of the at least one isolated fin while exposing the at least one sacrificial fin; and
performing a sacrificial etching process to remove the at least one sacrificial fin while maintaining the at least one isolated fin.

3. The method of claim 2 , wherein the sacrificial etching process removes exposed portions of the at least one isolated fin.

4. The method of claim 3 , wherein the at least one patterning assist feature is arranged according to a feature patterning table.

5. The method of claim 4 , wherein the feature patterning table is based on a distance between the at least one patterning assist feature and the at least one isolated fin.

6. The method of claim 5 , wherein the feature patterning table is based further on at least one of a number of the at least one patterning assist feature, and a width of the at least one patterning assist feature.

7. The method of claim 3 , wherein the at least one patterning assist feature is arranged according to an etching model.

8. The method of claim 7 , wherein the etching model is based on lithographic exposure patterns and a resist exposure and development characteristics of the masking layer.

9. A method of fabricating a semiconductor device, the method comprising:
forming a plurality of semiconductor fins on an upper surface of a semiconductor substrate, the plurality of fins including at least one isolated fin and at least one sacrificial fin;
forming a cut mask on the upper surface of the semiconductor substrate to cover the plurality of fins, and patterning the cut mask to expose the at least one sacrificial fin;
performing a first sacrificial cutting process to remove the at least one sacrificial fin and form a void on the upper surface of the substrate while maintaining the at least one isolated fin;
forming a patterning assist feature in the void such that the combination of the patterning assist feature and the at least one isolated fins defines a dense array pattern; and
performing an etching process to transfer the dense array pattern into the semiconductor substrate, the at least one patterning assist feature reducing the loading effect realized by the at least one isolated fin during the etching process.

10. The method of claim 9 , wherein the etching process is a reactive ion etching (RIE) process, and wherein the patterning assist feature realizes diffusion of reactive neutral species generated by the RIE process such that passivation to the sidewalls of the at least one isolated fin is reduced.

11. The method of claim 10 , wherein the cut mask exposes a portion of the at least one isolated fin, and the first sacrificial cutting process removes the exposed portion of the at least one isolated fin.

12. The method of claim 11 , further comprising performing a second sacrificial cutting process that removes the at least one-patterning assist feature to define an isolated semiconductor device including only the at least one isolated fin.

13. The method of claim 12 , wherein the printing patterning assist feature is arranged according to a feature patterning table.

14. The method of claim 13 , wherein the feature patterning table is based on at least one of a distance between the patterning assist feature and the at least one isolated fin, a number of the patterning assist feature, and a width of the at least one-patterning assist feature.

15. The method of claim 12 , wherein the patterning assist feature is arranged according to an etching model.

16. The method of claim 15 , wherein the etching model is based on lithographic exposure patterns and a resist exposure and development characteristics of masking layer.

17. A method of fabricating a semiconductor device, the method comprising:
forming a plurality of semiconductor fins on an upper surface of a semiconductor substrate, the plurality of fins extending along a first direction to define a length;
forming a gate stack on the plurality of semiconductor fins, the gate stack extending in the first direction to define a gate length and a second distance opposite the first direction to define a gate width;
identifying a gate extension portion located adjacent the plurality of semiconductor fins to receive an extended portion of the gate stack; and
forming a cutting pattern in the gate extension portion and on the extend portion of the gate stack; and
forming a semiconductor assist structure adjacent an isolated semiconductor included with the plurality of semiconductor fins.

18. The method of claim 17 , wherein the gate extension portion is removed according to the cutting pattern prior to forming the semiconductor assist structure.

19. The method of claim 18 , further comprising forming at least one cutting pattern on the plurality of semiconductor fins and at least one masking layer on the plurality of semiconductor fins, and etching the plurality of semiconductor fins according to the at least one cutting pattern and the at least one masking layer.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Dechene Daniel J
• Han Geng
• Mansfield Scott M
• Sieg Stuart A
• Yin Yunpeng

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title