Mechanisms for forming patterns using multiple lithography processes

Patent metadata

Field	Value
Publication number	US-9875906-B2
Application number	US-201615076199-A
Country	US
Kind code	B2
Filing date	Mar 21, 2016
Priority date	Mar 13, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A method for forming patterns in a semiconductor device includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; and forming a second feature in a second hard mask layer formed over the patterning-target layer. The first hard mask layer has a different etching selectivity from the second hard mask layer. The method further includes selectively removing a portion of the first feature within a first trench to form a reshaped first feature. In an embodiment, the first trench exposes a portion of the second feature, and the selectively removing of the first portion of the first feature does not etch the portion of the second feature.

First claim

What is claimed is:

1. A method for forming patterns in a semiconductor device, comprising:
providing a substrate and a patterning-target layer formed over the substrate;
forming a first feature in a first hard mask layer formed over the patterning-target layer;
forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; and
selectively removing a first portion of the first feature within a first trench, thereby forming a reshaped first feature.

2. The method of claim 1 , wherein the first trench exposes a portion of the second feature, and wherein the selectively removing of the first portion of the first feature does not etch the portion of the second feature.

3. The method of claim 1 , further comprising:
transferring the reshaped first feature and the second feature to the patterning-target layer.

4. The method of claim 1 , further comprising:
selectively removing a first portion of the second feature within a second trench, thereby forming a reshaped second feature.

5. The method of claim 4 , wherein the second trench exposes a second portion of the first feature, and wherein the selectively removing of the first portion of the second feature does not etch the second portion of the first feature.

6. The method of claim 4 , further comprising:
transferring the reshaped first feature and the reshaped second feature to the patterning-target layer.

7. The method of claim 1 , wherein the first feature is a line feature and the forming of the second feature is after the forming of the first feature, and wherein the forming of the second feature includes:
forming a buffer layer over the first hard mask layer and the patterning-target layer;
etching the buffer layer to form a buffer trench;
depositing the second hard mask layer to fill the buffer trench and to cover the buffer layer; and
removing an upper portion of the second hard mask layer to form the second feature in the second hard mask layer.

8. The method of claim 7 , wherein the removing of the upper portion of the second hard mask layer includes a chemical mechanical polish (CMP) method.

9. The method of claim 7 , wherein the removing of the upper portion of the second hard mask layer includes a selective etching process.

10. The method of claim 7 , further comprising:
removing the buffer layer using an etching process that is selectively tuned to remove the buffer layer while the first feature, the second feature, and the patterning-target layer remain substantially unchanged.

11. The method of claim 1 , wherein a thickness of the second feature is substantially similar to a thickness of the first feature.

12. The method of claim 1 , further comprising:
forming a resist layer over the first hard mask layer and the second hard mask layer; and
patterning the resist layer to form the first trench.

13. The method of claim 12 , further comprising:
forming a buffer layer between the resist layer and the first hard mask layer and the second hard mask layer; and
etching the buffer layer using the resist layer as an etching mask.

14. A method for forming patterns in a semiconductor device, comprising:
providing a substrate, a patterning-target layer over the substrate, and a first hard mask layer over the patterning-target layer, the first hard mask layer including a first material;
performing a first lithography to form a first line feature in the first hard mask layer;
forming a buffer layer over the first line feature and the patterning-target layer;
performing a second lithography to form a first trench in the buffer layer;
forming a second line feature in the first trench, the second line feature including a second material;
forming a first resist layer over the first and second line features;
performing a third lithography to form a second trench in the first resist layer; and
etching the first line feature within the second trench using the first resist layer as an etching mask, wherein the etching of the first line feature does not etch the second line feature.

15. The method of claim 14 , further comprising:
forming a second resist layer over the first and second line features;
performing a fourth lithography to form a third trench in the second resist layer;
etching the second line feature within the third trench using the second resist layer as an etching mask, wherein the etching of the second line feature does not etch the first line feature; and
etching the patterning-target layer using an etching mask that includes remaining portions of the first and second line features.

16. The method of claim 14 , wherein the first material includes titanium nitride, and
wherein the second material includes one or more materials selected from the group consisting of silicon nitride and silicon oxynitride.

17. The method of claim 14 , wherein the etching of the second line feature includes using one or more etching gases selected from the group consisting of carbon tetrafluoride, difluoromethane, and trifluoromethane, and wherein the etching of the first line feature includes using chlorine.

18. The method of claim 14 , wherein the forming of the second line feature includes:
depositing a second hard mask layer to fill in the first trench and to cover the buffer layer; and
removing an upper portion of the second hard mask layer, wherein the second line feature is part of remaining portions of the second hard mask layer.

19. A method for forming patterns in a semiconductor device, comprising:
forming a first feature in a first hard mask layer using a first lithography, the first hard mask layer being formed over a patterning-target layer;
forming a second feature in a second hard mask layer using a second lithography, the second hard mask layer being formed over the patterning-target layer;
forming a first trench in a first material layer formed over the first hard mask layer and the second hard mask layer; and
etching a portion of the first feature exposed within the first trench to form a reshaped first feature, wherein the etching of the portion of the first feature does not etch the second hard mask layer.

20. The method of claim 19 , further comprising:
etching the patterning-target layer based on the reshaped first feature of the first hard mask layer and further based on the second hard mask layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Shih-Ming

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title