Opening in the pad for bonding integrated passive device in InFO package

Patent metadata

Field	Value
Publication number	US-10165682-B2
Application number	US-201514979954-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

First claim

What is claimed is:

1. A package comprising:
a first conductive pad, with a plurality of openings penetrating through the first conductive pad, wherein all portions of the first conductive pad are electrically inter-coupled;
a dielectric layer encircling the first conductive pad, wherein the dielectric layer comprises portions filling the plurality of openings;
a first Under-Bump Metallurgy (UBM) comprising a first via portion extending into the dielectric layer to contact the first conductive pad;
a solder region over and contacting the first UBM; and
an integrated passive device, wherein the solder region bonds the first UBM to the integrated passive device.

2. The package of claim 1 further comprising:
a plurality of redistribution lines underlying the first conductive pad;
an encapsulating material underlying the plurality of redistribution lines;
a through-via encapsulated in the encapsulating material; and
a device die encapsulated in the encapsulating material.

3. The package of claim 1 , wherein the first conductive pad laterally extends beyond edges of the first UBM.

4. The package of claim 1 , wherein the plurality of openings is aligned to a ring, with the first conductive pad having an outer portion outside of the ring, and an inner portion inside the ring, and the first via portion has a bottom surface contacting a top surface of the inner portion of the first conductive pad.

5. The package of claim 1 , wherein the first UBM comprises a plurality of via portions contacting the first conductive pad, with the first via portion being one of the plurality of via portions.

6. The package of claim 1 , wherein the plurality of openings extends from a top surface of the first conductive pad to a bottom surface of the first conductive pad.

7. The package of claim 1 further comprising a second conductive pad, with an additional plurality of openings penetrating through the second conductive pad, and wherein the dielectric layer extends into the additional plurality of openings.

8. The package of claim 7 , wherein the first UBM further comprises a second via portion, with the second conductive pad contacting a bottom surface of the second via portion.

9. The package of claim 1 , wherein the integrated passive device comprises a first terminal and a second terminal, with the first UBM connected to the first terminal, and the package further comprises a second UBM connected to the second terminal.

10. The package of claim 1 , wherein the integrated passive device comprises a capacitor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Cheng-Hsien
• Wu Chi-Hsi
• Yu Chen-Hua
• Yeh Der-Chyang
• Chen Hsien-Wei
• Hsu Li-Han
• Wu Wei-Cheng

Classifications

• H05K2201/0969

  Apertured conductors · CPC title

• H05K2201/09381

  Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component · CPC title

• H05K2201/09136

  Means for correcting warpage · CPC title

• H05K2201/068

  wherein the coefficient of thermal expansion is important · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title